From patchwork Wed May 11 14:57:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 53813 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 50E65395A462 for ; Wed, 11 May 2022 14:58:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from gcc1-power7.osuosl.org (gcc1-power7.osuosl.org [140.211.15.137]) by sourceware.org (Postfix) with ESMTP id D23413835829 for ; Wed, 11 May 2022 14:57:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D23413835829 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=none smtp.mailfrom=gcc1-power7.osuosl.org Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 82F49124075E; Wed, 11 May 2022 14:57:21 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/3] rs6000: Remove Date: Wed, 11 May 2022 14:57:02 +0000 Message-Id: <663cfdb7086618d055a20f757900d537f25d4877.1652278190.git.segher@kernel.crashing.org> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: In-Reply-To: References: X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Segher Boessenkool , dje.gcc@gmail.com, "Kewen.Lin" Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The mode iterator can just use "d" always. 2022-05-11 Segher Boessenkool * config/rs6000/rs6000.md: Use d instead of . --- gcc/config/rs6000/rs6000.md | 117 +++++++++++++++++++++----------------------- 1 file changed, 57 insertions(+), 60 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 64049a6e521c..0100d67e9217 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -622,9 +622,6 @@ (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)") ; Iterator for ISA 3.0 supported floating point types (define_mode_iterator FP_ISA3 [SF DF]) -; SF/DF constraint for arithmetic on traditional floating point registers -(define_mode_attr Ff [(SF "f") (DF "d") (DI "d")]) - ; SF/DF constraint for arithmetic on VSX registers using instructions added in ; ISA 2.06 (power7). This includes instructions that normally target DF mode, ; but are used on SFmode, since internally SFmode values are kept in the DFmode @@ -4871,8 +4868,8 @@ (define_expand "abs2" "") (define_insn "*abs2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,")))] "TARGET_HARD_FLOAT" "@ fabs %0,%1 @@ -4880,10 +4877,10 @@ (define_insn "*abs2_fpr" [(set_attr "type" "fpsimple")]) (define_insn "*nabs2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") (neg:SFDF (abs:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ","))))] + (match_operand:SFDF 1 "gpc_reg_operand" "d,"))))] "TARGET_HARD_FLOAT" "@ fnabs %0,%1 @@ -4897,8 +4894,8 @@ (define_expand "neg2" "") (define_insn "*neg2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,")))] "TARGET_HARD_FLOAT" "@ fneg %0,%1 @@ -4913,9 +4910,9 @@ (define_expand "add3" "") (define_insn "*add3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa") - (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT" "@ fadd %0,%1,%2 @@ -4931,9 +4928,9 @@ (define_expand "sub3" "") (define_insn "*sub3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa") - (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT" "@ fsub %0,%1,%2 @@ -4949,9 +4946,9 @@ (define_expand "mul3" "") (define_insn "*mul3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa") - (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT" "@ fmul %0,%1,%2 @@ -4975,9 +4972,9 @@ (define_expand "div3" }) (define_insn "*div3_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa") - (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT" "@ fdiv %0,%1,%2 @@ -4986,8 +4983,8 @@ (define_insn "*div3_fpr" (set_attr "isa" "*,")]) (define_insn "*sqrt2_internal" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa") - (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",wa")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT && TARGET_PPC_GPOPT" "@ fsqrt %0,%1 @@ -5014,8 +5011,8 @@ (define_expand "sqrt2" ;; Floating point reciprocal approximation (define_insn "fre" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",wa")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_FRES))] "TARGET_" "@ @@ -5061,8 +5058,8 @@ (define_expand "remainder3" }) (define_insn "*rsqrt2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",wa")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")] UNSPEC_RSQRT))] "RS6000_RECIP_HAVE_RSQRTE_P (mode)" "@ @@ -5074,8 +5071,8 @@ (define_insn "*rsqrt2" ;; Floating point comparisons (define_insn "*cmp_fpr" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y") - (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" ",wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa")))] + (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "d,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa")))] "TARGET_HARD_FLOAT" "@ fcmpu %0,%1,%2 @@ -5277,9 +5274,9 @@ (define_expand "copysign3" ;; Use an unspec rather providing an if-then-else in RTL, to prevent the ;; compiler from optimizing -0.0 (define_insn "copysign3_fcpsgn" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",") - (match_operand:SFDF 2 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,") + (match_operand:SFDF 2 "gpc_reg_operand" "d,")] UNSPEC_COPYSIGN))] "TARGET_HARD_FLOAT && (TARGET_CMPB || VECTOR_UNIT_VSX_P (mode))" "@ @@ -6205,7 +6202,7 @@ (define_expand "fix_truncdi2" (define_insn "*fix_truncdi2_fctidz" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") - (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,")))] "TARGET_HARD_FLOAT && TARGET_FCFID" "@ fctidz %0,%1 @@ -6324,7 +6321,7 @@ (define_insn_and_split "fixuns_truncsi2_stfiwx" (define_insn "fixuns_truncdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") - (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d,")))] "TARGET_HARD_FLOAT && TARGET_FCTIDUZ" "@ fctiduz %0,%1 @@ -6474,7 +6471,7 @@ (define_expand "rs6000_set_fpscr_drn" (define_insn "fctiwz_" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") (unspec:DI [(fix:SI - (match_operand:SFDF 1 "gpc_reg_operand" ","))] + (match_operand:SFDF 1 "gpc_reg_operand" "d,"))] UNSPEC_FCTIWZ))] "TARGET_HARD_FLOAT" "@ @@ -6485,7 +6482,7 @@ (define_insn "fctiwz_" (define_insn "fctiwuz_" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wa") (unspec:DI [(unsigned_fix:SI - (match_operand:SFDF 1 "gpc_reg_operand" ","))] + (match_operand:SFDF 1 "gpc_reg_operand" "d,"))] UNSPEC_FCTIWUZ))] "TARGET_HARD_FLOAT && TARGET_FCTIWUZ" "@ @@ -6588,8 +6585,8 @@ (define_insn "lrintdi2" [(set_attr "type" "fp")]) (define_insn "btrunc2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,")] UNSPEC_FRIZ))] "TARGET_HARD_FLOAT && TARGET_FPRND" "@ @@ -6598,8 +6595,8 @@ (define_insn "btrunc2" [(set_attr "type" "fp")]) (define_insn "ceil2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,")] UNSPEC_FRIP))] "TARGET_HARD_FLOAT && TARGET_FPRND" "@ @@ -6608,8 +6605,8 @@ (define_insn "ceil2" [(set_attr "type" "fp")]) (define_insn "floor2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,")] UNSPEC_FRIM))] "TARGET_HARD_FLOAT && TARGET_FPRND" "@ @@ -10152,7 +10149,7 @@ (define_insn "*movqi_update3" (set_attr "indexed" "yes,no")]) (define_insn "*mov_update1" - [(set (match_operand:SFDF 3 "gpc_reg_operand" "=,") + [(set (match_operand:SFDF 3 "gpc_reg_operand" "=d,d") (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") (match_operand:P 2 "reg_or_short_operand" "r,I")))) (set (match_operand:P 0 "gpc_reg_operand" "=b,b") @@ -10171,7 +10168,7 @@ (define_insn "*mov_update1" (define_insn "*mov_update2" [(set (mem:SFDF (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") (match_operand:P 2 "reg_or_short_operand" "r,I"))) - (match_operand:SFDF 3 "gpc_reg_operand" ",")) + (match_operand:SFDF 3 "gpc_reg_operand" "d,d")) (set (match_operand:P 0 "gpc_reg_operand" "=b,b") (plus:P (match_dup 1) (match_dup 2)))] "TARGET_HARD_FLOAT && TARGET_UPDATE @@ -14142,11 +14139,11 @@ (define_expand "fma4" "") (define_insn "*fma4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa,wa") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa") (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" "%,wa,wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa,0") - (match_operand:SFDF 3 "gpc_reg_operand" ",0,wa")))] + (match_operand:SFDF 1 "gpc_reg_operand" "%d,wa,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0") + (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa")))] "TARGET_HARD_FLOAT" "@ fmadd %0,%1,%2,%3 @@ -14166,11 +14163,11 @@ (define_expand "fms4" "") (define_insn "*fms4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa,wa") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa") (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",wa,wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa,0") - (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" ",0,wa"))))] + (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0") + (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa"))))] "TARGET_HARD_FLOAT" "@ fmsub %0,%1,%2,%3 @@ -14213,12 +14210,12 @@ (define_expand "nfma4" "") (define_insn "*nfma4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa,wa") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa") (neg:SFDF (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",wa,wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa,0") - (match_operand:SFDF 3 "gpc_reg_operand" ",0,wa"))))] + (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0") + (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa"))))] "TARGET_HARD_FLOAT" "@ fnmadd %0,%1,%2,%3 @@ -14239,13 +14236,13 @@ (define_expand "nfms4" "") (define_insn "*nfmssf4_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,wa,wa") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa,wa") (neg:SFDF (fma:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ",wa,wa") - (match_operand:SFDF 2 "gpc_reg_operand" ",wa,0") + (match_operand:SFDF 1 "gpc_reg_operand" "d,wa,wa") + (match_operand:SFDF 2 "gpc_reg_operand" "d,wa,0") (neg:SFDF - (match_operand:SFDF 3 "gpc_reg_operand" ",0,wa")))))] + (match_operand:SFDF 3 "gpc_reg_operand" "d,0,wa")))))] "TARGET_HARD_FLOAT" "@ fnmsub %0,%1,%2,%3