From patchwork Wed May 25 20:25:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: will schmidt X-Patchwork-Id: 54387 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 42C5F3830653 for ; Wed, 25 May 2022 20:26:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 42C5F3830653 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653510403; bh=Zgr+SFM2Vj+/lqg/bKxmBbj6h+OqpLEJyS4BZlOGnuo=; h=Subject:To:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=P2T1sRsMg/NZ5PHqBJdyLJ+6qel2XnknPnhjxmq9ZqsTW3Ga298+/2gfEArMtVAqC bEsaDBzp/YgdVAoHBe3pZC8D5Tw0QgJaYtoVAetzxweC4fVwdtsjxH72J8JRuiW221 lNeUL/ztt1Kn+UAicgRzPadJOBbzJpOPRh8qWY2U= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 535233830665 for ; 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Wed, 25 May 2022 20:25:31 GMT Received: from b03cxnp07028.gho.boulder.ibm.com (b03cxnp07028.gho.boulder.ibm.com [9.17.130.15]) by ppma04wdc.us.ibm.com with ESMTP id 3g93uyrev0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 May 2022 20:25:31 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 24PKPUVg29425972 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 25 May 2022 20:25:30 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4C46DBE056; Wed, 25 May 2022 20:25:30 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A7ABEBE04F; Wed, 25 May 2022 20:25:29 +0000 (GMT) Received: from lexx (unknown [9.160.34.81]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 25 May 2022 20:25:29 +0000 (GMT) Message-ID: <6591013b62270c39c912f0c13c4cd12ffbaf75a2.camel@vnet.ibm.com> Subject: [PATCH, rs6000] Clean up the option_mask defines (part 1) To: Segher Boessenkool , David Edelsohn Date: Wed, 25 May 2022 15:25:29 -0500 X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jLAu1uC28KwTyS3amZCGu14suuxdXcCY X-Proofpoint-ORIG-GUID: lUDdHoueLUOL0d3lrpYnTRjOANZTMtan X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-25_05,2022-05-25_02,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2205250095 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: will schmidt Reply-To: will schmidt Cc: GCC Patches Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH, rs6000] Clean up the option_mask defines Hi, We have an assortment of MASK and OPTION_MASK #defines throughout the rs6000 code, MASK_ALTIVEC and OPTION_MASK_ALTIVEC as an example. We currently #define the MASK_ entries to their OPTION_MASK_ equivalents so the two names could be used interchangeably. The mapping is in place from when we switched from using target_flags to rs6000_isa_flags via commit 4d9675496a28ef6184f2a9c3ac5e6e3ea63606c1 in 2012. This patch converts the references for most of the lingering MASK_* values to OPTION_MASK_* and removes the now redundant defines. I have split this into multiple parts due to size. Regtested OK on power10. OK for trunk? gcc/ * rs6000.h (MASK_ALTIVEC, MASK_CMPB, MASK_CRYPTO MASK_DLMZB, MASK_EABI, MASK_FPRND, MASK_ISEL MASK_MFCRF, MASK_MULHW, MASK_POPCNTB, MASK_PPC_GFXOPT MASK_PPC_GPOPT): Remove defines. (RS6000_BTM_ALTIVEC, RS6000_BTM_CMPB, RS6000_BTM_CRYPTO, RS6000_BTM_FRE, RS6000_BTM_FRES, RS6000_BTM_FRSQRTE, RS6000_BTM_FRSQRTES, RS6000_BTM_CELL) : Redefine using OPTION_MASK_ instead of MASK_. * rs6000-cpus.def (RS6000_CPU) Update macro calls to use OPTION_MASK_ instead of MASK_. * rs6000.cc (rs6000_darwin_file_start): Update mapping[] table entries to use OPTION_MASK_PPC_GPOPT, OPTION_MASK_MFCRF, OPTION_MASK_ALTIVEC instead of their MASK_ variants. * rs6000-c.cc : Update comment to reference OPTION_MASK_GFXOPT. * aix71.h (TARGET_DEFAULT): Update define to use OPTION_MASK_ instead of MASK_. * darwin.h (TARGET_DEFAULT): Same. * darwin64-biarch.h (TARGET_DEFAULT): Same. * default64.h (TARGET_DEFAULT): Same. * eabi.h (TARGET_DEFAULT): Same. * eabialtivec.h (TARGET_DEFAULT): Same. * linuxaltivec.h (TARGET_DEFAULT): Same. * vxworks.h (TARGET_DEFAULT): Same. diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h index 57e07bcc65ee..8c2ec5d36375 100644 --- a/gcc/config/rs6000/aix71.h +++ b/gcc/config/rs6000/aix71.h @@ -135,13 +135,15 @@ do { \ #include "rs6000-cpus.def" #undef RS6000_CPU #undef TARGET_DEFAULT #ifdef RS6000_BI_ARCH -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #else -#define TARGET_DEFAULT (MASK_PPC_GPOPT | MASK_PPC_GFXOPT | MASK_MFCRF) +#define TARGET_DEFAULT (OPTION_MASK_PPC_GPOPT | OPTION_MASK_PPC_GFXOPT \ + | OPTION_MASK_MFCRF) #endif #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_POWER7 #undef PROCESSOR_DEFAULT64 diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index b5cef42610f7..86556ccbbf58 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -365,11 +365,11 @@ /* Default target flag settings. Despite the fact that STMW/LMW serializes, it's still a big code size win to use them. Use FSEL by default as well. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_PPC_GFXOPT) +#define TARGET_DEFAULT (MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) /* Darwin always uses IBM long double, never IEEE long double. */ #undef TARGET_IEEEQUAD #define TARGET_IEEEQUAD 0 diff --git a/gcc/config/rs6000/darwin64-biarch.h b/gcc/config/rs6000/darwin64-biarch.h index 57b0fab084e3..6a700c61c4c2 100644 --- a/gcc/config/rs6000/darwin64-biarch.h +++ b/gcc/config/rs6000/darwin64-biarch.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_POWERPC64 | MASK_64BIT \ - | MASK_MULTIPLE | MASK_PPC_GFXOPT) + | MASK_MULTIPLE | OPTION_MASK_PPC_GFXOPT) #undef DARWIN_ARCH_SPEC #define DARWIN_ARCH_SPEC "%{m32:ppc;:ppc64}" /* Actually, there's really only 970 as an active option. */ diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h index 4bf0feef2f8e..08b58c965d19 100644 --- a/gcc/config/rs6000/default64.h +++ b/gcc/config/rs6000/default64.h @@ -27,9 +27,10 @@ along with GCC; see the file COPYING3. If not see #define TARGET_DEFAULT (ISA_2_7_MASKS_SERVER | MASK_POWERPC64 | MASK_64BIT | MASK_LITTLE_ENDIAN) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower8" #else #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_PPC_GFXOPT | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) +#define TARGET_DEFAULT (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT \ + | OPTION_MASK_MFCRF | MASK_POWERPC64 | MASK_64BIT) #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mpower4" #endif diff --git a/gcc/config/rs6000/eabi.h b/gcc/config/rs6000/eabi.h index e58283fe5d4e..367de7bc2700 100644 --- a/gcc/config/rs6000/eabi.h +++ b/gcc/config/rs6000/eabi.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ /* Add -meabi to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_EABI +#define TARGET_DEFAULT OPTION_MASK_EABI /* Invoke an initializer function to set up the GOT. */ #define NAME__MAIN "__eabi" #define INVOKE__main diff --git a/gcc/config/rs6000/eabialtivec.h b/gcc/config/rs6000/eabialtivec.h index 63cb00fa8054..23cef799a045 100644 --- a/gcc/config/rs6000/eabialtivec.h +++ b/gcc/config/rs6000/eabialtivec.h @@ -19,11 +19,11 @@ along with GCC; see the file COPYING3. If not see . */ /* Add -meabi and -maltivec to target flags. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_ALTIVEC) +#define TARGET_DEFAULT (OPTION_MASK_EABI | OPTION_MASK_ALTIVEC) #undef ASM_DEFAULT_EXTRA #define ASM_DEFAULT_EXTRA " %{!mvsx:%{!maltivec:%{!no-maltivec:-maltivec}}}" #undef SUBSUBTARGET_OVERRIDE_OPTIONS diff --git a/gcc/config/rs6000/linuxaltivec.h b/gcc/config/rs6000/linuxaltivec.h index d2557ca57adb..55bae1188369 100644 --- a/gcc/config/rs6000/linuxaltivec.h +++ b/gcc/config/rs6000/linuxaltivec.h @@ -20,14 +20,14 @@ . */ /* Override rs6000.h and sysv4.h definition. */ #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN) #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_ALTIVEC | MASK_LITTLE_ENDIAN) +#define TARGET_DEFAULT (OPTION_MASK_ALTIVEC | MASK_LITTLE_ENDIAN) #else #undef TARGET_DEFAULT -#define TARGET_DEFAULT MASK_ALTIVEC +#define TARGET_DEFAULT OPTION_MASK_ALTIVEC #endif #undef ASM_DEFAULT_EXTRA #define ASM_DEFAULT_EXTRA " %{!mvsx:%{!maltivec:%{!mno-altivec:-maltivec}}}" diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 9c8cbd7a66e4..9572dd58d907 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -382,11 +382,11 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, 3. If either of the above two conditions apply except that the TARGET_DEFAULT macro is defined to equal zero, and TARGET_POWERPC64 and a) BYTES_BIG_ENDIAN and the flag to be enabled is either - MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64" + OPTION_MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64" target), or b) !BYTES_BIG_ENDIAN and the flag to be enabled is either MASK_POWERPC64 or it is one of the flags included in ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target). diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index 963947f69392..ca78bd8cf89f 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -176,82 +176,92 @@ where the arguments are the fields of struct rs6000_ptt. */ RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) -RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("476", PROCESSOR_PPC476, - MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB - | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("476fp", PROCESSOR_PPC476, - MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_MULHW | MASK_DLMZB) +RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("405fp", PROCESSOR_PPC405, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("440fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | OPTION_MASK_MULHW + | OPTION_MASK_DLMZB) +RS6000_CPU ("464fp", PROCESSOR_PPC440, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("476", PROCESSOR_PPC476, MASK_SOFT_FLOAT | OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND + | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("476fp", PROCESSOR_PPC476, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND + | OPTION_MASK_CMPB | OPTION_MASK_MULHW | OPTION_MASK_DLMZB) RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE) -RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT) -RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT) -RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT) -RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT) +RS6000_CPU ("602", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("603", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("603e", PROCESSOR_PPC603, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("604", PROCESSOR_PPC604, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("604e", PROCESSOR_PPC604e, OPTION_MASK_PPC_GFXOPT) +RS6000_CPU ("620", PROCESSOR_PPC620, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("630", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("740", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT) +RS6000_CPU ("750", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) -RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL) -RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL) -RS6000_CPU ("a2", PROCESSOR_PPCA2, - MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB - | MASK_NO_UPDATE) +RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) +RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | OPTION_MASK_ISEL) +RS6000_CPU ("a2", PROCESSOR_PPCA2, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64 + | OPTION_MASK_POPCNTB | OPTION_MASK_CMPB | MASK_NO_UPDATE) RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) -RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL) +RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, OPTION_MASK_PPC_GFXOPT + | OPTION_MASK_ISEL) RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e5500", PROCESSOR_PPCE5500, - MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) + MASK_POWERPC64 | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ISEL) RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 - | MASK_MFCRF | MASK_ISEL) + | OPTION_MASK_MFCRF | OPTION_MASK_ISEL) RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) RS6000_CPU ("970", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) + POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF + | MASK_POWERPC64) RS6000_CPU ("cell", PROCESSOR_CELL, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) + POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF + | MASK_POWERPC64) RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) -RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) +RS6000_CPU ("G3", PROCESSOR_PPC750, OPTION_MASK_PPC_GFXOPT) RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) -RS6000_CPU ("G5", PROCESSOR_POWER4, - POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) -RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB) -RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF) -RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB) -RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) -RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) -RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT - | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND - | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) +RS6000_CPU ("G5", PROCESSOR_POWER4, POWERPC_7400_MASK | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_MFCRF | MASK_POWERPC64) +RS6000_CPU ("titan", PROCESSOR_TITAN, OPTION_MASK_MULHW | OPTION_MASK_DLMZB) +RS6000_CPU ("power3", PROCESSOR_PPC630, OPTION_MASK_PPC_GFXOPT + | MASK_POWERPC64) +RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF) +RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB) +RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB + | OPTION_MASK_FPRND) +RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | MASK_DFP + | MASK_RECIP_PRECISION) +RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB + | OPTION_MASK_FPRND | OPTION_MASK_CMPB | MASK_DFP + | MASK_RECIP_PRECISION) RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM) RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) -RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER - | OPTION_MASK_HTM) -RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) +RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT + | MASK_POWERPC64) +RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 + | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM) +RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d4defc855d02..200bef3f822e 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -20727,15 +20727,15 @@ rs6000_darwin_file_start (void) const char *arg; const char *name; HOST_WIDE_INT if_set; } mapping[] = { { "ppc64", "ppc64", MASK_64BIT }, - { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, + { "970", "ppc970", OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64 }, { "power4", "ppc970", 0 }, { "G5", "ppc970", 0 }, { "7450", "ppc7450", 0 }, - { "7400", "ppc7400", MASK_ALTIVEC }, + { "7400", "ppc7400", OPTION_MASK_ALTIVEC }, { "G4", "ppc7400", 0 }, { "750", "ppc750", 0 }, { "740", "ppc750", 0 }, { "G3", "ppc750", 0 }, { "604e", "ppc604e", 0 }, diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 3b8941a86584..ef7f10e4efee 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -505,36 +505,24 @@ extern int rs6000_vector_align[]; && (TARGET_P9_MINMAX || !flag_trapping_math)) /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. For now map OPTION_MASK_ back into MASK_. */ -#define MASK_ALTIVEC OPTION_MASK_ALTIVEC -#define MASK_CMPB OPTION_MASK_CMPB -#define MASK_CRYPTO OPTION_MASK_CRYPTO #define MASK_DFP OPTION_MASK_DFP #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE -#define MASK_DLMZB OPTION_MASK_DLMZB -#define MASK_EABI OPTION_MASK_EABI #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW -#define MASK_FPRND OPTION_MASK_FPRND #define MASK_P8_FUSION OPTION_MASK_P8_FUSION #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT #define MASK_HTM OPTION_MASK_HTM -#define MASK_ISEL OPTION_MASK_ISEL -#define MASK_MFCRF OPTION_MASK_MFCRF #define MASK_MMA OPTION_MASK_MMA -#define MASK_MULHW OPTION_MASK_MULHW #define MASK_MULTIPLE OPTION_MASK_MULTIPLE #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR #define MASK_P9_MISC OPTION_MASK_P9_MISC -#define MASK_POPCNTB OPTION_MASK_POPCNTB #define MASK_POPCNTD OPTION_MASK_POPCNTD -#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT -#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN #define MASK_UPDATE OPTION_MASK_UPDATE #define MASK_VSX OPTION_MASK_VSX @@ -2251,24 +2239,24 @@ extern int frame_pointer_needed; /* Builtin targets. For now, we reuse the masks for those options that are in target flags, and pick a random bit for ldbl128, which isn't in target_flags. */ #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ -#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ -#define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ +#define RS6000_BTM_ALTIVEC OPTION_MASK_ALTIVEC /* VMX/altivec vectors. */ +#define RS6000_BTM_CMPB OPTION_MASK_CMPB /* ISA 2.05: compare bytes. */ #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ -#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ +#define RS6000_BTM_CRYPTO OPTION_MASK_CRYPTO /* crypto funcs. */ #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ -#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ -#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ -#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ -#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ +#define RS6000_BTM_FRE OPTION_MASK_POPCNTB /* FRE instruction. */ +#define RS6000_BTM_FRES OPTION_MASK_PPC_GFXOPT /* FRES instruction. */ +#define RS6000_BTM_FRSQRTE OPTION_MASK_PPC_GFXOPT /* FRSQRTE instruction. */ +#define RS6000_BTM_FRSQRTES OPTION_MASK_POPCNTB /* FRSQRTES instruction. */ #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ -#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ +#define RS6000_BTM_CELL OPTION_MASK_FPRND /* Target is cell powerpc. */ #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ diff --git a/gcc/config/rs6000/vxworks.h b/gcc/config/rs6000/vxworks.h index 4f6d116929b6..6f11de6c5792 100644 --- a/gcc/config/rs6000/vxworks.h +++ b/gcc/config/rs6000/vxworks.h @@ -225,11 +225,11 @@ along with GCC; see the file COPYING3. If not see #undef LINK_SPEC #define LINK_SPEC VXWORKS_LINK_SPEC " " VXWORKS_RELAX_LINK_SPEC #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_EABI | MASK_STRICT_ALIGN) +#define TARGET_DEFAULT (OPTION_MASK_EABI | MASK_STRICT_ALIGN) #undef PROCESSOR_DEFAULT #define PROCESSOR_DEFAULT PROCESSOR_PPC604 /* Only big endian PPC is supported by VxWorks. */