From patchwork Thu Jun 1 20:01:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 70475 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 09CF83858C50 for ; Thu, 1 Jun 2023 20:03:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 09CF83858C50 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1685649797; bh=bVpwLsNKMxmgA5ZPnGlLzv2jai1a7bbDvPP7zPgExSY=; h=Subject:To:Cc:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=tRDWmpmMEBdJPPT/qVSZ3xGtqjzkS6kLgOueHSedDdQiGo40NXOKFRix7TD72a9CD dKMBmHyHqXVmsi9zkgEDEPuk9254x2LHBgw5HB2HD1vz7n/KL2ndVkqWMcFS9MYL8Y wBa5kfqY92Ls4tqCWZn/W7hBdo24y6UnDbPrkUTM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 37DC93857735 for ; Thu, 1 Jun 2023 20:01:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 37DC93857735 Received: from pps.filterd (m0356517.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 351JwdMS007021; Thu, 1 Jun 2023 20:01:49 GMT Received: from ppma05wdc.us.ibm.com (1b.90.2fa9.ip4.static.sl-reverse.com [169.47.144.27]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qy1y3g21a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 01 Jun 2023 20:01:48 +0000 Received: from pps.filterd (ppma05wdc.us.ibm.com [127.0.0.1]) by ppma05wdc.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 351IAtSv012703; Thu, 1 Jun 2023 20:01:47 GMT Received: from smtprelay07.wdc07v.mail.ibm.com ([9.208.129.116]) by ppma05wdc.us.ibm.com (PPS) with ESMTPS id 3qu9g63n2g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 01 Jun 2023 20:01:47 +0000 Received: from smtpav05.wdc07v.mail.ibm.com (smtpav05.wdc07v.mail.ibm.com [10.39.53.232]) by smtprelay07.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 351K1jx263963544 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 Jun 2023 20:01:45 GMT Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 969CC5805D; Thu, 1 Jun 2023 20:01:45 +0000 (GMT) Received: from smtpav05.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EFAD15805F; Thu, 1 Jun 2023 20:01:44 +0000 (GMT) Received: from li-e362e14c-2378-11b2-a85c-87d605f3c641.ibm.com (unknown [9.61.7.186]) by smtpav05.wdc07v.mail.ibm.com (Postfix) with ESMTP; Thu, 1 Jun 2023 20:01:44 +0000 (GMT) Message-ID: <602fbdd3b3407e834713953d0d23c1ce47173dc7.camel@us.ibm.com> Subject: [PATCH] rs6000: Fix arguments for __builtin_altivec_tr_stxvrwx, __builtin_altivec_tr_stxvrhx To: Peter Bergner , "Kewen.Lin" Cc: Segher Boessenkool , gcc-patches@gcc.gnu.org, cel@us.ibm.com Date: Thu, 01 Jun 2023 13:01:44 -0700 In-Reply-To: <95fb95f2-24af-5a1e-d086-ae786bb7c770@linux.ibm.com> References: <95fb95f2-24af-5a1e-d086-ae786bb7c770@linux.ibm.com> X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: mWvvHRMCupUYVVGiGIvDuSc_a603ylfu X-Proofpoint-GUID: mWvvHRMCupUYVVGiGIvDuSc_a603ylfu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-01_08,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=893 spamscore=0 mlxscore=0 bulkscore=0 adultscore=0 phishscore=0 suspectscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306010172 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Carl Love via Gcc-patches From: Carl Love Reply-To: Carl Love Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Kewen, Segher, Peter: The following patch is a redo of the previous "rs6000: Fix __builtin_vec_xst_trunc definition" patch. This patch fixes the argument in the two builtin definitions __builtin_altivec_tr_stxvrwx and __builtin_altivec_tr_stxvrhx. It also adds with a testcase to validate the related builtins which have the third argument of char *, short *, int * and long long *. I have tested the patch on Power 10 with no regressions. Please let me know if this patch is acceptable for mainline. Carl ------------------------------------------------------------ rs6000: Fix arguments for __builtin_altivec_tr_stxvrwx, __builtin_altivec_tr_stxvrhx The third argument for __builtin_altivec_tr_stxvrhx should be short * not int *. Similarly, the third argument for __builtin_altivec_tr_stxvrwx should be int * not short *. This patch fixes the arguments in the two builtins. A runnable test case is added to test the __builtin_altivec_tr_stxvrbx, __builtin_altivec_tr_stxvrhx, __builtin_altivec_tr_stxvrwx and __builtin_altivec_tr_stxvrdx builtins. gcc/ * config/rs6000/rs6000-builtins.def (__builtin_altivec_tr_stxvrhx, __builtin_altivec_tr_stxvrwx): Fix type of third argument. gcc/testsuite/ * gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c: New test for __builtin_altivec_tr_stxvrbx, __builtin_altivec_tr_stxvrhx, __builtin_altivec_tr_stxvrwx, __builtin_altivec_tr_stxvrdx. --- gcc/config/rs6000/rs6000-builtins.def | 4 +- .../builtin_altivec_tr_stxvr_runnable.c | 107 ++++++++++++++++++ 2 files changed, 109 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 638d0bc72ca..d7839f2e06b 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -3161,10 +3161,10 @@ void __builtin_altivec_tr_stxvrbx (vsq, signed long, signed char *); TR_STXVRBX vsx_stxvrbx {stvec} - void __builtin_altivec_tr_stxvrhx (vsq, signed long, signed int *); + void __builtin_altivec_tr_stxvrhx (vsq, signed long, signed short *); TR_STXVRHX vsx_stxvrhx {stvec} - void __builtin_altivec_tr_stxvrwx (vsq, signed long, signed short *); + void __builtin_altivec_tr_stxvrwx (vsq, signed long, signed int *); TR_STXVRWX vsx_stxvrwx {stvec} void __builtin_altivec_tr_stxvrdx (vsq, signed long, signed long long *); diff --git a/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c b/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c new file mode 100644 index 00000000000..46014d83535 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c @@ -0,0 +1,107 @@ +/* Test of __builtin_vec_xst_trunc */ + +/* { dg-do run { target power10_hw } } */ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-mdejagnu-cpu=power10 -save-temps" } */ + +#include +#include +#include +#include +#include + +#define DEBUG 0 + +vector signed __int128 store_data = + { (__int128) 0x8ACE000000000000 << 64 | (__int128) 0xfedcba9876543217ULL}; + +union conv_t { + vector signed __int128 vsi128; + unsigned long long ull[2]; +} conv; + +void abort (void); + + +int +main () { + int i; + signed long sl; + signed char sc, expected_sc; + signed short ss, expected_ss; + signed int si, expected_si; + signed long long int sll, expected_sll; + signed char *psc; + signed short *pss; + signed int *psi; + signed long long int *psll; + +#if DEBUG + val.vsi128 = store_data; + printf("Data to store [%d] = 0x%llx %llx\n", i, val.ull[1], val.ull[0]); +#endif + + psc = ≻ + pss = &ss; + psi = &si; + psll = &sll; + + sl = 1; + sc =0xA1; + expected_sc = 0xA1; + __builtin_altivec_tr_stxvrbx (store_data, sl, psc); + + if (expected_sc != sc & 0xFF) +#if DEBUG + printf(" ERROR: Signed char = 0x%x doesn't match expected value 0x%x\n", + sc & 0xFF, expected_sc); +#else + abort(); +#endif + + sl = 1; + ss = 0x52; + expected_ss = 0x1752; + __builtin_altivec_tr_stxvrhx (store_data, sl, pss); + + if (expected_ss != ss & 0xFFFF) +#if DEBUG + printf(" ERROR: Signed short = 0x%x doesn't match expected value 0x%x\n", + ss, expected_ss) & 0xFFFF; +#else + abort(); +#endif + + sl = 1; + si = 0x21; + expected_si = 0x54321721; + __builtin_altivec_tr_stxvrwx (store_data, sl, psi); + + if (expected_si != si) +#if DEBUG + printf(" ERROR: Signed int = 0x%x doesn't match expected value 0x%x\n", + si, expected_si); +#else + abort(); +#endif + + sl = 1; + sll = 0x12FFULL; + expected_sll = 0xdcba9876543217FF; + __builtin_altivec_tr_stxvrdx (store_data, sl, psll); + + if (expected_sll != sll) +#if DEBUG + printf(" ERROR: Signed long long int = 0x%llx doesn't match expected value 0x%llx\n", + sll, expected_sll); +#else + abort(); +#endif + + return 0; +} + +/* { dg-final { scan-assembler-times {\mstxvrbx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstxvrhx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstxvrwx\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstxvrdx\M} 1 } } */