diff mbox series

[v2,01/07] RISC-V: autovec: Add new predicates and function prototypes

Message ID 5dcf3e4a-5c4f-161e-7ae6-b4cd0708cf8f@rivosinc.com
State Superseded, archived
Headers
Series RISC-V: autovec: Add auto-vectorization support |

Commit Message

Michael Collison March 6, 2023, 3:13 a.m. UTC 
  This patch adds foundational support in the form of:

1. New predicates

2. New function prototypes

3. Exporting emit_vlmax_vsetvl to global scope

4. Add a new command line option -mriscv_vector_lmu

2023-03-02  Michael Collison <collison@rivosinc.com>
                     Juzhe Zhong <juzhe.zhong@rivai.ai>

                 * config/riscv/riscv-protos.h (riscv_classify_vlmul_field):
                 New external declaration.
                 (riscv_vector_preferred_simd_mode): Ditto.
                 (riscv_tuple_mode_p): Ditto.
                 (riscv_vector_mask_mode_p): Ditto.
                 (riscv_classify_nf): Ditto.
                 (riscv_vlmul_regsize): Ditto.
                 (riscv_vector_preferred_simd_mode): Ditto.
                 (riscv_vector_get_mask_mode): Ditto.
                 (emit_vlmax_vsetvl): Ditto.
                 (get_mask_policy_no_pred): Ditto.
                 (get_tail_policy_no_pred): Ditto.
                 * config/riscv/riscv-opts.h (riscv_vector_bits_enum): 
New enum.
                 (riscv_vector_lmul_enum): Ditto.
                 (vlmul_field_enum): Ditto.
                 * config/riscv/riscv-v.cc (emit_vlmax_vsetvl):
                 Remove static scope.
                 * config/riscv/riscv.opt (riscv_vector_lmul):
                 New option -mriscv_vector_lmul.
                 * config/riscv/predicates.md (p_reg_or_const_csr_operand):
                 New predicate.
                 (vector_reg_or_const_dup_operand): Ditto.

---
  gcc/config/riscv/predicates.md  | 13 +++++++++++
  gcc/config/riscv/riscv-opts.h   | 40 +++++++++++++++++++++++++++++++++
  gcc/config/riscv/riscv-protos.h | 15 +++++++++++++
  gcc/config/riscv/riscv-v.cc     |  2 +-
  gcc/config/riscv/riscv.opt      | 20 +++++++++++++++++
  5 files changed, 89 insertions(+), 1 deletion(-)

  Use hardware floating-point divide and square root instructions.
diff mbox series

Patch

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 0d9d7701c7e..19aa5e12920 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -264,6 +264,14 @@ 
  })

  ;; Predicates for the V extension.
+(define_special_predicate "p_reg_or_const_csr_operand"
+  (match_code "reg, subreg, const_int")
+{
+  if (CONST_INT_P (op))
+    return satisfies_constraint_K (op);
+  return GET_MODE (op) == Pmode;
+})
+
  (define_special_predicate "vector_length_operand"
    (ior (match_operand 0 "pmode_register_operand")
         (match_operand 0 "const_csr_operand")))
@@ -291,6 +299,11 @@ 
    (and (match_code "const_vector")
         (match_test "rtx_equal_p (op, 
riscv_vector::gen_scalar_move_mask (GET_MODE (op)))")))

+(define_predicate "vector_reg_or_const_dup_operand"
+  (ior (match_operand 0 "register_operand")
+       (match_test "const_vec_duplicate_p (op)
+       && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))")))
+
  (define_predicate "vector_mask_operand"
    (ior (match_operand 0 "register_operand")
         (match_operand 0 "vector_all_trues_mask_operand")))
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index ff398c0a2ae..c6b6d84fce4 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -67,6 +67,46 @@  enum stack_protector_guard {
    SSP_GLOBAL            /* global canary */
  };

+/* RVV vector register sizes.  */
+enum riscv_vector_bits_enum
+{
+  RVV_SCALABLE,
+  RVV_NOT_IMPLEMENTED = RVV_SCALABLE,
+  RVV_64 = 64,
+  RVV_128 = 128,
+  RVV_256 = 256,
+  RVV_512 = 512,
+  RVV_1024 = 1024,
+  RVV_2048 = 2048,
+  RVV_4096 = 4096,
+  RVV_8192 = 8192,
+  RVV_16384 = 16384,
+  RVV_32768 = 32768,
+  RVV_65536 = 65536
+};
+
+/* vectorization factor.  */
+enum riscv_vector_lmul_enum
+{
+  RVV_LMUL1 = 1,
+  RVV_LMUL2 = 2,
+  RVV_LMUL4 = 4,
+  RVV_LMUL8 = 8
+};
+
+enum vlmul_field_enum
+{
+  VLMUL_FIELD_000, /* LMUL = 1.  */
+  VLMUL_FIELD_001, /* LMUL = 2.  */
+  VLMUL_FIELD_010, /* LMUL = 4.  */
+  VLMUL_FIELD_011, /* LMUL = 8.  */
+  VLMUL_FIELD_100, /* RESERVED.  */
+  VLMUL_FIELD_101, /* LMUL = 1/8.  */
+  VLMUL_FIELD_110, /* LMUL = 1/4.  */
+  VLMUL_FIELD_111, /* LMUL = 1/2.  */
+  MAX_VLMUL_FIELD
+};
+
  #define MASK_ZICSR    (1 << 0)
  #define MASK_ZIFENCEI (1 << 1)

diff --git a/gcc/config/riscv/riscv-protos.h 
b/gcc/config/riscv/riscv-protos.h
index 88a6bf5442f..6a486a1cd61 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -217,4 +217,19 @@  const unsigned int RISCV_BUILTIN_SHIFT = 1;
  /* Mask that selects the riscv_builtin_class part of a function code.  */
  const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1;

+/* Routines implemented in riscv-v.cc.  */
+
+namespace riscv_vector {
+extern unsigned int riscv_classify_vlmul_field (enum machine_mode m);
+extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode,
+                              unsigned vf);
+extern bool riscv_tuple_mode_p (machine_mode);
+extern bool riscv_vector_mask_mode_p (machine_mode);
+extern int riscv_classify_nf (machine_mode);
+extern int riscv_vlmul_regsize (machine_mode);
+extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode);
+extern rtx emit_vlmax_vsetvl (machine_mode vmode);
+extern rtx get_mask_policy_no_pred ();
+extern rtx get_tail_policy_no_pred ();
+}
  #endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index d65c65b26cd..2d2de6e4a6c 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -109,7 +109,7 @@  const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT 
minval,
        && IN_RANGE (INTVAL (elt), minval, maxval));
  }

-static rtx
+rtx
  emit_vlmax_vsetvl (machine_mode vmode)
  {
    rtx vl = gen_reg_rtx (Pmode);
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 95535235354..27005fb0f4a 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -70,6 +70,26 @@  Enum(abi_type) String(lp64f) Value(ABI_LP64F)
  EnumValue
  Enum(abi_type) String(lp64d) Value(ABI_LP64D)

+Enum
+Name(riscv_vector_lmul) Type(enum riscv_vector_lmul_enum)
+The possible vectorization factor:
+
+EnumValue
+Enum(riscv_vector_lmul) String(1) Value(RVV_LMUL1)
+
+EnumValue
+Enum(riscv_vector_lmul) String(2) Value(RVV_LMUL2)
+
+EnumValue
+Enum(riscv_vector_lmul) String(4) Value(RVV_LMUL4)
+
+EnumValue
+Enum(riscv_vector_lmul) String(8) Value(RVV_LMUL8)
+
+mriscv-vector-lmul=
+Target RejectNegative Joined Enum(riscv_vector_lmul) 
Var(riscv_vector_lmul) Init(RVV_LMUL1)
+-mriscv-vector-lmul=<lmul>    Set the vf using lmul in auto-vectorization.
+
  mfdiv
  Target Mask(FDIV)