From patchwork Thu Oct 7 10:51:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 45952 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0F1CF3858022 for ; Thu, 7 Oct 2021 10:52:04 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa4.mentor.iphmx.com (esa4.mentor.iphmx.com [68.232.137.252]) by sourceware.org (Postfix) with ESMTPS id 32BF43858C60 for ; Thu, 7 Oct 2021 10:51:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 32BF43858C60 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: GEc+czk6tBH0OBweC2nn3t7UfFKCR4YXswCi+EjTZtxyfpGXys23pmihManvBEOjWITiTBEqL4 UYFc5vc1ZjgAvVJrCaimgqzzJnb0RHxdT27DQW0A2ynD1aBkbrnaWg+Wj1kaHcxX+VLBNHvYqw kcs5fihGBch0nwOOb470AJ8bt0At1BbD19BkSH1TwQAUUjjQYxv74vzcN5zdNBuvQzoGNHdAh/ veW7cHXcwuGHAxnUEENvMOHFd224Bfd9GbR7cASHzz3kGU2gGqwBxlIZpdvLYPBpv8EhsUSAJH qON9y13IAvuJ4FXa22Nk9d+/ X-IronPort-AV: E=Sophos;i="5.85,354,1624348800"; d="scan'208";a="66926038" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa4.mentor.iphmx.com with ESMTP; 07 Oct 2021 02:51:46 -0800 IronPort-SDR: zBKc3f0EF7h8fB0LIRjxUJJSZG4mavwaCVKvd3OLYEbTrD059tIlHTNkdDmEhRKNXtP8yXFsRB C1SE66sIdL8Z8RkExUyH5MAlVtDAOZATpKZW1B1gflWDoZN8Q1qqu5HTjk2Zem4hxbes8Cgpwq lkwbJaQzMh68bPmNXxIwWwq6/5wa4/Sme9jfYLW/CTS1/GZPL8YIPZny0RZqWHFGJaAo+uN35y +A2CwIMdio8cz4P5Mocs+2egA1lMsZZXvJo9PUaGXJEKNo8m4c7J+HrWfoBprNFman+eJtXjAY fwk= Message-ID: <4c4999ac-ba8d-4246-db20-dd3a1395958e@codesourcery.com> Date: Thu, 7 Oct 2021 11:51:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.1.2 Content-Language: en-GB From: Andrew Stubbs Subject: [committed] amdgcn: Fix assembler version incompatibility To: "gcc-patches@gcc.gnu.org" X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) To svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" I've committed this patch to fix another case of LLVM assembler incompatibility. Marcel previously posted a patch to fix up the global_load and global_store instructions, following a non-backwards-compatible change in the assembler. https://gcc.gnu.org/pipermail/gcc-patches/2021-June/572987.html This patch fixes up another instance of the same problem, this time in the gather and scatter instruction patterns. The fix is needed for LLVM 12 & 13. There is not change in behaviour for LLVM 9. Andrew amdgcn: Fix assembler version incompatibility This is another case of the global_load instruction format changing in LLVM (because they fixed a bug). The configure test is already in place to detect what is needed. gcc/ChangeLog: * config/gcn/gcn-valu.md (gather_insn_2offsets): Apply HAVE_GCN_ASM_GLOBAL_LOAD_FIXED. (scatter_insn_2offsets): Likewise. diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 84ff67508b99..01fdce64d423 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -827,8 +827,12 @@ (define_insn "gather_insn_2offsets" /* Work around assembler bug in which a 64-bit register is expected, but a 32-bit value would be correct. */ int reg = REGNO (operands[2]) - FIRST_VGPR_REG; - sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" - "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc); + if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED) + sprintf (buf, "global_load%%o0\t%%0, v%d, %%1 offset:%%3%s\;" + "s_waitcnt\tvmcnt(0)", reg, glc); + else + sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" + "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc); } else gcc_unreachable (); @@ -958,8 +962,12 @@ (define_insn "scatter_insn_2offsets" /* Work around assembler bug in which a 64-bit register is expected, but a 32-bit value would be correct. */ int reg = REGNO (operands[1]) - FIRST_VGPR_REG; - sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s", - reg, reg + 1, glc); + if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED) + sprintf (buf, "global_store%%s3\tv%d, %%3, %%0 offset:%%2%s", + reg, glc); + else + sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s", + reg, reg + 1, glc); } else gcc_unreachable ();