diff mbox series

[committed,PR105032] LRA: modify loop condition to find reload insns for hard reg splitting

Message ID 4a7d72ce-55db-3fe2-b08b-62960810a3ec@redhat.com
State Committed
Headers
Series [committed,PR105032] LRA: modify loop condition to find reload insns for hard reg splitting |

Commit Message

Vladimir Makarov March 30, 2022, 5:14 p.m. UTC 
  The following patch fixes

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105032

The patch was successfully bootstrapped and tested on x86-64.

Comments

Uros Bizjak March 30, 2022, 7:18 p.m. UTC | #1 
On Wed, Mar 30, 2022 at 7:15 PM Vladimir Makarov via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> The following patch fixes
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105032
>
> The patch was successfully bootstrapped and tested on x86-64.

diff --git a/gcc/testsuite/gcc.target/i386/pr105032.c
b/gcc/testsuite/gcc.target/i386/pr105032.c
new file mode 100644
index 00000000000..57b21d3cd7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr105032.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-w" } */
+/* { dg-additional-options "-m32" { target x86_64-*-* } } */

Please don't use -m32 in options, but instead conditionally compile
the testcase with

/* { dg-do compile { target ia32 } } */

Uros.
Vladimir Makarov March 30, 2022, 8:13 p.m. UTC | #2 
On 2022-03-30 15:18, Uros Bizjak wrote:
> On Wed, Mar 30, 2022 at 7:15 PM Vladimir Makarov via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
>> The following patch fixes
>>
>> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105032
>>
>> The patch was successfully bootstrapped and tested on x86-64.
> diff --git a/gcc/testsuite/gcc.target/i386/pr105032.c
> b/gcc/testsuite/gcc.target/i386/pr105032.c
> new file mode 100644
> index 00000000000..57b21d3cd7a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr105032.c
> @@ -0,0 +1,36 @@
> +/* { dg-do compile } */
> +/* { dg-options "-w" } */
> +/* { dg-additional-options "-m32" { target x86_64-*-* } } */
>
> Please don't use -m32 in options, but instead conditionally compile
> the testcase with

Sorry for may be a stupid question.  I am interesting what are the 
reasons for this.  Is it just for saving computer cycles?

I think the test is important therefore I'd like to run the test on 
x86-64 too because people rarely test i686 target.

> /* { dg-do compile { target ia32 } } */
diff mbox series

Patch

commit 25de4889c16fec80172a5e2d1825f3ff505d0cc4
Author: Vladimir N. Makarov <vmakarov@redhat.com>
Date:   Wed Mar 30 13:03:44 2022 -0400

    [PR105032] LRA: modify loop condition to find reload insns for hard reg splitting
    
    When trying to split hard reg live range to assign hard reg to a reload
    pseudo, LRA searches for reload insns of the reload pseudo
    assuming a specific order of the reload insns.  This order is violated if
    reload involved in inheritance transformation. In such case, the loop used
    for reload insn searching can become infinite.  The patch fixes this.
    
    gcc/ChangeLog:
    
            PR middle-end/105032
            * lra-assigns.cc (find_reload_regno_insns): Modify loop condition.
    
    gcc/testsuite/ChangeLog:
    
            PR middle-end/105032
            * gcc.target/i386/pr105032.c: New.

diff --git a/gcc/lra-assigns.cc b/gcc/lra-assigns.cc
index af30a673142..486e94f2006 100644
--- a/gcc/lra-assigns.cc
+++ b/gcc/lra-assigns.cc
@@ -1730,7 +1730,8 @@  find_reload_regno_insns (int regno, rtx_insn * &start, rtx_insn * &finish)
     {
       for (prev_insn = PREV_INSN (start_insn),
 	     next_insn = NEXT_INSN (start_insn);
-	   insns_num != 1 && (prev_insn != NULL || next_insn != NULL); )
+	   insns_num != 1 && (prev_insn != NULL
+			      || (next_insn != NULL && second_insn == NULL)); )
 	{
 	  if (prev_insn != NULL)
 	    {
diff --git a/gcc/testsuite/gcc.target/i386/pr105032.c b/gcc/testsuite/gcc.target/i386/pr105032.c
new file mode 100644
index 00000000000..57b21d3cd7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr105032.c
@@ -0,0 +1,36 @@ 
+/* { dg-do compile } */
+/* { dg-options "-w" } */
+/* { dg-additional-options "-m32" { target x86_64-*-* } } */
+
+typedef unsigned int size_t;	
+__extension__ typedef long int __off_t;
+typedef __off_t off_t;
+static void *__sys_mmap(void *addr, size_t length, int prot, int flags, int fd,
+			off_t offset)
+{
+  offset >>= 12;
+  return (void *)({ long _ret;
+      register long _num asm("eax") = (192);
+      register long _arg1 asm("ebx") = (long)(addr);
+      register long _arg2 asm("ecx") = (long)(length);
+      register long _arg3 asm("edx") = (long)(prot);
+      register long _arg4 asm("esi") = (long)(flags);
+      register long _arg5 asm("edi") = (long)(fd);
+      long _arg6 = (long)(offset);
+      asm volatile ("pushl	%[_arg6]\n\t"
+		    "pushl	%%ebp\n\t"
+		    "movl	4(%%esp), %%ebp\n\t"
+		    "int	$0x80\n\t"
+		    "popl	%%ebp\n\t"
+		    "addl	$4,%%esp\n\t"
+		    : "=a"(_ret)
+		    : "r"(_num), "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4),"r"(_arg5), [_arg6]"m"(_arg6)
+		    : "memory", "cc" );
+      _ret; });
+}
+
+int main(void)
+{
+  __sys_mmap(((void *)0), 0x1000, 0x1 | 0x2, 0x20 | 0x02, -1, 0);
+  return 0;
+}