diff mbox series

[committed] hppa: Revise -mdisable-fpregs option and add new -msoft-mult option

Message ID 3f70a280-683a-2e68-7be9-ff69a1dd8ee0@bell.net
State Committed
Headers
Series [committed] hppa: Revise -mdisable-fpregs option and add new -msoft-mult option |

Commit Message

John David Anglin Oct. 24, 2021, 6:35 p.m. UTC 
  The Linux kernel on hppa is built with -mdisable-fpregs to inhibit the use of the floating-point
registers.  However, I noticed that the 64-bit kernel was using floating-point registers for hardware
integer multiplication (xmpyu).  It turned out this was because various DImode routines in libgcc
(e.g., __muldi3) were built with hardware integer multiplication enabled.  This turned out not to
be a problem as currently the kernel saves the floating-point registers in syscalls, etc.  But it
was the intention that the floating-point registers not be used in kernel code.

It also turned out that -mdisable-fpregs didn't disable use of the floating-point registers as documented.
The -msoft-float option does that.  What the kernel needs is an option to disable hardware integer multiplication.
This is sufficient to avoid the use of the floating-point registers.  It appears -mdisable-fpregs was originally
intended to disable use of xmpyu but its operation got confused with time.

The attached change has been tested on hppa2.0w-hp-hpux11.11, hppa64-hp-hpux11.11 and hppa-unknown-linux-gnu.
I also checked that libgcc can be built with -msoft-mult.  It currently is not configured to build successfully
with -msoft-float.

Committed to trunk and gcc-11 branch.

Dave
---
Revise -mdisable-fpregs option and add new -msoft-mult option

The behavior of the -mdisable-fpregs is confusing in that it doesn't
disable the use of the floating-point registers in all situations.
The -msoft-float disables the use of the floating-point registers in
all situations.  The Linux kernel only needs to disable use of the
xmpyu instruction to avoid using the floating-point registers.

This change revises the -mdisable-fpregs option to disable the use of
the floating-point registers in all situations.  It is now equivalent
to the -msoft-float option.  A new -msoft-mult option is added to
disable use of the xmpyu instruction.  The libgcc library can be
compiled with the -msoft-mult option to avoid using hardware integer
multiplication.

2021-10-24  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

	* config/pa/pa-d.c (pa_d_handle_target_float_abi): Don't check
	TARGET_DISABLE_FPREGS.
	* config/pa/pa.c (fix_range): Use MASK_SOFT_FLOAT instead of
	MASK_DISABLE_FPREGS.
	(hppa_rtx_costs): Don't check TARGET_DISABLE_FPREGS.  Adjust
	cost of hardware integer multiplication.
	(pa_conditional_register_usage): Don't check TARGET_DISABLE_FPREGS.
	* config/pa/pa.h (INT14_OK_STRICT): Likewise.
	* config/pa/pa.md: Don't check TARGET_DISABLE_FPREGS. Check
	TARGET_SOFT_FLOAT in patterns that use xmpyu instruction.
	* config/pa/pa.opt (mdisable-fpregs): Change target mask to
	SOFT_FLOAT.  Revise comment.
	(msoft-float): New option.
diff mbox series

Patch

diff --git a/gcc/config/pa/pa-d.c b/gcc/config/pa/pa-d.c
index 6802738e85b..14ef8cae343 100644
--- a/gcc/config/pa/pa-d.c
+++ b/gcc/config/pa/pa-d.c
@@ -47,7 +47,7 @@  pa_d_handle_target_float_abi (void)
  {
    const char *abi;

-  if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
+  if (TARGET_SOFT_FLOAT)
      abi = "soft";
    else
      abi = "hard";
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index d13021ad94a..21b812e9be7 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -497,7 +497,7 @@  fix_range (const char *const_str)
        break;

    if (i > FP_REG_LAST)
-    target_flags |= MASK_DISABLE_FPREGS;
+    target_flags |= MASK_SOFT_FLOAT;
  }

  /* Implement the TARGET_OPTION_OVERRIDE hook.  */
@@ -1578,14 +1578,14 @@  hppa_rtx_costs (rtx x, machine_mode mode, int outer_code,
  	}
        else if (mode == DImode)
  	{
-	  if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
-	    *total = COSTS_N_INSNS (32);
+	  if (TARGET_PA_11 && !TARGET_SOFT_FLOAT && !TARGET_SOFT_MULT)
+	    *total = COSTS_N_INSNS (25);
  	  else
  	    *total = COSTS_N_INSNS (80);
  	}
        else
  	{
-	  if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
+	  if (TARGET_PA_11 && !TARGET_SOFT_FLOAT && !TARGET_SOFT_MULT)
  	    *total = COSTS_N_INSNS (8);
  	  else
  	    *total = COSTS_N_INSNS (20);
@@ -10627,7 +10627,7 @@  pa_conditional_register_usage (void)
        for (i = 33; i < 56; i += 2)
  	fixed_regs[i] = call_used_regs[i] = 1;
      }
-  if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
+  if (TARGET_SOFT_FLOAT)
      {
        for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
  	fixed_regs[i] = call_used_regs[i] = 1;
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index fbb96045a51..7a313d617b0 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -833,7 +833,6 @@  extern int may_call_alloca;

  #define INT14_OK_STRICT \
    (TARGET_SOFT_FLOAT                                                   \
-   || TARGET_DISABLE_FPREGS                                            \
     || (TARGET_PA_20 && !TARGET_ELF32))

  /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index c1864524b38..ea6da457fcb 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -5384,7 +5384,7 @@ 
    "
  {
    operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
-  if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
+  if (TARGET_PA_11 && !TARGET_SOFT_FLOAT && !TARGET_SOFT_MULT)
      {
        rtx scratch = gen_reg_rtx (DImode);
        operands[1] = force_reg (SImode, operands[1]);
@@ -5402,7 +5402,7 @@ 
    [(set (match_operand:DI 0 "register_operand" "=f")
  	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
  		 (zero_extend:DI (match_operand:SI 2 "register_operand" "f"))))]
-  "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
+  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT"
    "xmpyu %1,%2,%0"
    [(set_attr "type" "fpmuldbl")
     (set_attr "length" "4")])
@@ -5411,7 +5411,7 @@ 
    [(set (match_operand:DI 0 "register_operand" "=f")
  	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
  		 (match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
+  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && !TARGET_64BIT"
    "xmpyu %1,%R2,%0"
    [(set_attr "type" "fpmuldbl")
     (set_attr "length" "4")])
@@ -5420,7 +5420,7 @@ 
    [(set (match_operand:DI 0 "register_operand" "=f")
  	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
  		 (match_operand:DI 2 "uint32_operand" "f")))]
-  "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
+  "TARGET_PA_11 && ! TARGET_SOFT_FLOAT && ! TARGET_SOFT_MULT && TARGET_64BIT"
    "xmpyu %1,%2R,%0"
    [(set_attr "type" "fpmuldbl")
     (set_attr "length" "4")])
@@ -5457,8 +5457,8 @@ 
  		 (match_operand:DI 2 "register_operand" "")))]
    "! optimize_size
     && TARGET_PA_11
-   && ! TARGET_DISABLE_FPREGS
-   && ! TARGET_SOFT_FLOAT"
+   && ! TARGET_SOFT_FLOAT
+   && ! TARGET_SOFT_MULT"
    "
  {
    rtx low_product = gen_reg_rtx (DImode);
@@ -7805,7 +7805,7 @@  add,l %2,%3,%3\;bv,n %%r0(%3)"
        if (GET_CODE (op) == SYMBOL_REF)
  	{
  	  /* Handle special call to buggy powf function.  */
-	  if (TARGET_HPUX && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT
+	  if (TARGET_HPUX && !TARGET_SOFT_FLOAT
  	      && !strcmp (targetm.strip_name_encoding (XSTR (op, 0)), "powf"))
  	    call_powf = true;

@@ -10260,7 +10260,7 @@  add,l %2,%3,%3\;bv,n %%r0(%3)"
  {
    enum memmodel model;

-  if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
+  if (TARGET_64BIT || TARGET_SOFT_FLOAT)
      FAIL;

    model = memmodel_from_int (INTVAL (operands[2]));
@@ -10276,7 +10276,7 @@  add,l %2,%3,%3\;bv,n %%r0(%3)"
    [(set (match_operand:DI 0 "register_operand" "=r")
          (mem:DI (match_operand:SI 1 "register_operand" "r")))
     (clobber (match_scratch:DI 2 "=f"))]
-  "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
+  "!TARGET_64BIT && !TARGET_SOFT_FLOAT"
    "{fldds|fldd} 0(%1),%2\n\t{fstds|fstd} %2,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0\n\t{ldws|ldw} -12(%%sp),%R0"
    [(set_attr "type" "move")
     (set_attr "length" "16")])
@@ -10299,7 +10299,7 @@  add,l %2,%3,%3\;bv,n %%r0(%3)"
  	DONE;
      }

-  if (TARGET_64BIT || TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
+  if (TARGET_64BIT || TARGET_SOFT_FLOAT)
      FAIL;

    model = memmodel_from_int (INTVAL (operands[2]));
@@ -10317,7 +10317,7 @@  add,l %2,%3,%3\;bv,n %%r0(%3)"
    [(set (mem:DI (match_operand:SI 0 "register_operand" "r,r"))
          (match_operand:DI 1 "reg_or_0_operand" "M,r"))
     (clobber (match_scratch:DI 2 "=X,f"))]
-  "!TARGET_64BIT && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT"
+  "!TARGET_64BIT && !TARGET_SOFT_FLOAT"
    "@
     {fstds|fstd} %%fr0,0(%0)
     {stws|stw} %1,-16(%%sp)\n\t{stws|stw} %R1,-12(%%sp)\n\t{fldds|fldd} -16(%%sp),%2\n\t{fstds|fstd} %2,0(%0)"
diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt
index 09660c47d88..47995f73e65 100644
--- a/gcc/config/pa/pa.opt
+++ b/gcc/config/pa/pa.opt
@@ -50,8 +50,8 @@  Target Var(TARGET_COHERENT_LDCW) Init(1)
  Use ldcw/ldcd coherent cache-control hint.

  mdisable-fpregs
-Target Mask(DISABLE_FPREGS)
-Disable FP regs.
+Target Mask(SOFT_FLOAT)
+Disable FP regs.  Equivalent to -msoft-float.

  mdisable-indexing
  Target Mask(DISABLE_INDEXING)
@@ -143,6 +143,10 @@  msoft-float
  Target Mask(SOFT_FLOAT)
  Use software floating point.

+msoft-mult
+Target Mask(SOFT_MULT)
+Use software integer multiplication.
+
  msnake
  Target RejectNegative
  Generate PA1.1 code.