From patchwork Thu Apr 20 04:34:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 68051 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A779C3858C00 for ; Thu, 20 Apr 2023 04:34:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by sourceware.org (Postfix) with ESMTPS id DB18E3858D37 for ; Thu, 20 Apr 2023 04:34:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DB18E3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-52160b73bdfso412377a12.1 for ; Wed, 19 Apr 2023 21:34:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1681965279; x=1684557279; h=subject:to:from:content-language:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=CZgZl3b+E5wwS/6DftmegQyYTyEKWKAQafdnrqrl7xc=; b=KsmxuP9sSy9gY38PtWKRNlUTci/stnpPgujNFLCVPAt9q/Y03DNtCUaphnbOPVQW4+ XxDNSPtXfryuiIKNKpRC5+rLPa+MYjVsn5bQhwFGhuX4O+6IA5azgKMPeSHC099oe+4+ myW1+k53Iuhm1IKq7NqoO2vQjU8wCmYWNZvORwC5tMEWp+T1CgGjUD9ndSBz1tVuCNEM 038lmCVf4D4OvL7p3ooq2Q8gCoztwET+dXI+Wf7Csj8qaqCwcltt4hNpkn9PfxIP+cIU SiqBuypokfV9n1/4Mn6Pi/uk2SI1OBZH763h0L/AG8iBXFlc5/Puu0murDr+QwaYVg7+ ehIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681965279; x=1684557279; h=subject:to:from:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=CZgZl3b+E5wwS/6DftmegQyYTyEKWKAQafdnrqrl7xc=; b=O/Tt+e/W18WKfad9Kf7vBbdSZuc/YOU8jL2kqnVKNxwAMsddvlybzy4A6ad9I2AJHc cbj0LnwwrrcS5gS9FopzgUH/m7BH+kI+01B02/AnZh6SU48hiSHR9D/dWT0DEgAj8ZME HQXNOWQ9emmpp1FhHc1kCeN/DHg627+/9r/JsObrP3sHM9bCJO4Mx+vEupcCwvb5Ap1j lDAiJ094AvTD+E7+4VggCiaZ9ak/s1273rSVyAGe1oPtm3XEsLYny7RutJ1lW+m2vMFP hFX4maib1GDjDnitRceSjQO9rwG8MaxAjzTbirmWhHpL5iUqpHQjTcpvkzy1jiZ3rF0+ RhNw== X-Gm-Message-State: AAQBX9cD3edTsiDdZ6nm+m15fKPzkWXpt6m0Qd5I+ctoqhjPTboQ6xNQ u4Mb3wiQ5myFB0s7j8aJU1PJFF2gU2o2CnJlMSo= X-Google-Smtp-Source: AKy350Y7r464e65995b16d6IIgcS4s5I/QeB5G72y7nO1a8DaJqw1YaZv6cB3YuR0lFRakhEjemcHQ== X-Received: by 2002:a17:90a:f591:b0:247:13fc:2e2f with SMTP id ct17-20020a17090af59100b0024713fc2e2fmr316621pjb.34.1681965278993; Wed, 19 Apr 2023 21:34:38 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::99f? ([2601:681:8600:13d0::99f]) by smtp.gmail.com with ESMTPSA id u1-20020a17090ae00100b002471f9a010dsm2150546pjy.21.2023.04.19.21.34.36 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Apr 2023 21:34:36 -0700 (PDT) Message-ID: <3ee750e7-d3f5-12cc-4885-bbe2f6290861@ventanamicro.com> Date: Wed, 19 Apr 2023 22:34:34 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Content-Language: en-US From: Jeff Law To: "gcc-patches@gcc.gnu.org" Subject: [RFA] [PR target/108248] [RISC-V] Break down some bitmanip insn types X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This is primarily Raphael's work. All I did was adjust it to apply to the trunk and add the new types to generic.md's scheduling model. The basic idea here is to make sure we have the ability to schedule the bitmanip instructions with a finer degree of control. Some of the bitmanip instructions are likely to have differing scheduler characteristics across different implementations. So rather than assign these instructions a generic "bitmanip" type, this patch assigns them a type based on their RTL code by using the iterator for the type. Naturally we have to add a few new types. It affects clz, ctz, cpop, min, max. We didn't do this for things like shNadd, single bit manipulation, etc. We certainly could if the needs presents itself. I threw all the new types into the generic_alu bucket in the generic scheduling model. Seems as good a place as any. Someone who knows the sifive uarch should probably add these types (and bitmanip) to the sifive scheduling model. We also noticed that the recently added orc.b didn't have a type at all. So we added it as a generic bitmanip type. This has been bootstrapped in a gcc-12 base and I've built and run the testsuite without regressions on the trunk. Given it was primarily Raphael's work I could probably approve & commit it. But I'd like to give the other RISC-V folks a chance to chime in. OK for the trunk? Jeff PR target/108248 gcc/ * config/riscv/bitmanip.md (clz, ctz, pcnt, min, max patterns): Use as the type to allow for fine grained control of scheduling these insns. * config/riscv/generic.md (generic_alu): Add bitmanip, clz, ctz, pcnt, min, max. * config/riscv/riscv.md (type attribute): Add types for clz, ctz, pcnt, signed and unsigned min/max. diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 388ef662820..44ad350c747 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -241,7 +241,7 @@ (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_ZBB" "%~\t%0,%1" - [(set_attr "type" "bitmanip") + [(set_attr "type" "") (set_attr "mode" "SI")]) (define_insn "*disi2" @@ -250,7 +250,7 @@ (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r"))))] "TARGET_64BIT && TARGET_ZBB" "w\t%0,%1" - [(set_attr "type" "bitmanip") + [(set_attr "type" "") (set_attr "mode" "SI")]) (define_insn "*di2" @@ -258,7 +258,7 @@ (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBB" "\t%0,%1" - [(set_attr "type" "bitmanip") + [(set_attr "type" "") (set_attr "mode" "DI")]) (define_insn "*zero_extendhi2_bitmanip" @@ -357,7 +357,8 @@ [(set (match_operand:X 0 "register_operand" "=r") (unspec:X [(match_operand:X 1 "register_operand" "r")] UNSPEC_ORC_B))] "TARGET_ZBB" - "orc.b\t%0,%1") + "orc.b\t%0,%1" + [(set_attr "type" "bitmanip")]) (define_expand "bswapdi2" [(set (match_operand:DI 0 "register_operand") @@ -406,7 +407,7 @@ (match_operand:X 2 "reg_or_0_operand" "rJ")))] "TARGET_ZBB" "\t%0,%1,%z2" - [(set_attr "type" "bitmanip")]) + [(set_attr "type" "")]) ;; Optimize the common case of a SImode min/max against a constant ;; that is safe both for sign- and zero-extension. diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md index b98d0ae5258..db4fabbbd92 100644 --- a/gcc/config/riscv/generic.md +++ b/gcc/config/riscv/generic.md @@ -27,7 +27,7 @@ (define_insn_reservation "generic_alu" 1 (and (eq_attr "tune" "generic") - (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move")) + (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,smin,smax,umin,umax,clz,ctz,cpop")) "alu") (define_insn_reservation "generic_load" 3 diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index bc384d9aedf..15fbc5fe583 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -344,6 +344,7 @@ "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, + min,max,minu,maxu,clz,ctz,cpop, atomic,condmove,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,