From patchwork Mon Oct 17 23:47:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 58964 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 32D5C385828C for ; Mon, 17 Oct 2022 23:48:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 32D5C385828C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666050509; bh=gsCOSgavVIfvWGBzBQIRMjr96PhIx4VcPPyf6Zd0zYU=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=QqzLwVKpR1DgnLo2pIqWt91f9qpwnJ+oW0kHMBpPYey88VAcBQ4Ou6KGeyuDGQZjC 3/EBzxenLOgrYa2hqlPwJWc1xMg+xkM0hFSfmaMgtx0gz5NTU7RZxAx6rQXmjWoj5E aXI/5S9WLjqsoJyPv+CN1PYy0kzHyhdZxAFSWr2U= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by sourceware.org (Postfix) with ESMTPS id CE86D3858D3C for ; Mon, 17 Oct 2022 23:47:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CE86D3858D3C Received: by mail-pj1-x1034.google.com with SMTP id h12so12442261pjk.0 for ; Mon, 17 Oct 2022 16:47:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=subject:from:to:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=gsCOSgavVIfvWGBzBQIRMjr96PhIx4VcPPyf6Zd0zYU=; b=ReQBk9/1M+cuP9x5ofZZ50PpVP0si8ITr3u2j+eDIX5Bzd69/I0hRgSMA4GpkhnCtK OQylklmb1wlFSsaAxIt0sYVT7dc+qOjyXSqjK/naOqa8HkEJzDqlLmYVMkOh4gdIOi3/ NIF08HKxBS1YRa1lw2eJHf44nZhoOo9OWFqoSMYA6e5gqa3zy94Iw6HZArY5ylEC0xjF HtT1FFqHq5/wLihM7KCmvkgFV9lrPQbh4uieV8OF8gYCxm+axZy3eWnbB8TX7/h+LNJw RNZMoogDDf/V8r6ggpF2wbcMNxdOln+KCx1dIDKEke2xPoE6eIdO7Y4y/0TDpCXk8aSa yMJw== X-Gm-Message-State: ACrzQf0++XJ/3BZtJf6d7jYk0US7uwIxRbp9ZcItTxenJacaXlEBlxQn 43E9K8TyrylaHmUTfbx8EKZ9+PJ/wk0= X-Google-Smtp-Source: AMsMyM71pgrhkpP5TPMcc9OAIOCsCYbHgtibJot+Sdqz6mbvMmjfWbtnwzVJqi5jLekrqkjQYDIvQw== X-Received: by 2002:a17:90b:1b03:b0:20d:ac3b:f1dd with SMTP id nu3-20020a17090b1b0300b0020dac3bf1ddmr26500484pjb.121.1666050437533; Mon, 17 Oct 2022 16:47:17 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id v6-20020a632f06000000b0046497308480sm6833153pgv.77.2022.10.17.16.47.16 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 16:47:17 -0700 (PDT) Message-ID: <3aa2cc41-0ad2-e106-56d4-f839ae2c1078@gmail.com> Date: Mon, 17 Oct 2022 17:47:16 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Subject: [committed] More infrastructure to avoid bogus RTL on H8 X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jeff Law via Gcc-patches From: Jeff Law Reply-To: Jeff Law Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Continuing the work to add constraints to avoid invalid RTL  with autoinc addressing modes.  Specifically this patch adds  the memory constraints similar to the pdp11. Pushed to the trunk, Jeff commit 19859bd72119708c85cc6976b3547738be6f5b1c Author: Jeff Law Date: Mon Oct 17 19:42:27 2022 -0400 More infrastructure to avoid bogus RTL on H8. Continuing the work to add constraints to avoid invalid RTL with autoinc addressing modes. Specifically this patch adds the memory constraints similar to the pdp11. gcc/ * config/h8300/constraints.md (Za..Zh): New constraints for autoinc addresses using a specific register. * config/h8300/h8300.cc (pre_incdec_with_reg): New function. * config/h8300/h8300-protos.h (pre_incdec_with_reg): Add prototype. diff --git a/gcc/config/h8300/constraints.md b/gcc/config/h8300/constraints.md index 6eaffc16975..7e6681c4492 100644 --- a/gcc/config/h8300/constraints.md +++ b/gcc/config/h8300/constraints.md @@ -241,3 +241,11 @@ (define_register_constraint "Z7" "NOT_SP_REGS" "@internal") +(define_constraint "Za" "@internal" (match_test "pre_incdec_with_reg (op, 0)")) +(define_constraint "Zb" "@internal" (match_test "pre_incdec_with_reg (op, 1)")) +(define_constraint "Zc" "@internal" (match_test "pre_incdec_with_reg (op, 2)")) +(define_constraint "Zd" "@internal" (match_test "pre_incdec_with_reg (op, 3)")) +(define_constraint "Ze" "@internal" (match_test "pre_incdec_with_reg (op, 4)")) +(define_constraint "Zf" "@internal" (match_test "pre_incdec_with_reg (op, 5)")) +(define_constraint "Zg" "@internal" (match_test "pre_incdec_with_reg (op, 6)")) +(define_constraint "Zh" "@internal" (match_test "pre_incdec_with_reg (op, 7)")) diff --git a/gcc/config/h8300/h8300-protos.h b/gcc/config/h8300/h8300-protos.h index e9d434c0d5a..8c989495c29 100644 --- a/gcc/config/h8300/h8300-protos.h +++ b/gcc/config/h8300/h8300-protos.h @@ -100,6 +100,7 @@ extern int h8300_initial_elimination_offset (int, int); extern int h8300_regs_ok_for_stm (int, rtx[]); extern int h8300_hard_regno_rename_ok (unsigned int, unsigned int); extern bool h8300_move_ok (rtx, rtx); +extern bool pre_incdec_with_reg (rtx, int); struct cpp_reader; extern void h8300_pr_interrupt (struct cpp_reader *); diff --git a/gcc/config/h8300/h8300.cc b/gcc/config/h8300/h8300.cc index be3e385c91e..ce0702edecb 100644 --- a/gcc/config/h8300/h8300.cc +++ b/gcc/config/h8300/h8300.cc @@ -5531,6 +5531,32 @@ h8300_ok_for_sibcall_p (tree fndecl, tree) return 1; } + +/* Return TRUE if OP is a PRE_INC or PRE_DEC + instruction using REG, FALSE otherwise. */ + +bool +pre_incdec_with_reg (rtx op, int reg) +{ + /* OP must be a MEM. */ + if (GET_CODE (op) != MEM) + return false; + + /* The address must be a PRE_INC or PRE_DEC. */ + op = XEXP (op, 0); + if (GET_CODE (op) != PRE_DEC && GET_CODE (op) != PRE_INC) + return false; + + /* It must be a register that is being incremented + or decremented. */ + op = XEXP (op, 0); + if (!REG_P (op)) + return false; + + /* Finally, check that the register number matches. */ + return REGNO (op) == reg; +} + /* Initialize the GCC target structure. */ #undef TARGET_ATTRIBUTE_TABLE