diff mbox series

rs6000: Fix LE code gen for vec_cnt[lt]z_lsbb [PR95082]

Message ID 218bbb49-1974-ea1f-9109-997a86a6443e@linux.ibm.com
State Committed
Commit 3f30f2d1dbb3228b8468b26239fe60c2974ce2ac
Headers
Series rs6000: Fix LE code gen for vec_cnt[lt]z_lsbb [PR95082] |

Commit Message

Li, Pan2 via Gcc-patches Jan. 19, 2022, 5:25 p.m. UTC 
  Hi!

https://gcc.gnu.org/PR95082 demonstrates that we don't generate correct code for
vec_cntlz_lsbb and vec_cnttz_lsbb for little-endian targets.  This patch corrects
the problem by marking the built-ins as bif_is_endian and using the correct
target patterns for each endianness.  Note that the default patterns are for
little endian, and the overridden patterns in rs6000-builtin.cc are for big
endian.

Bootstrapped and tested on powerpc64le-linux-gnu with no regressions.  Is this
okay for trunk, and eventually for backport to GCC 11?

Thanks!
Bill


2022-01-18  Bill Schmidt  <wschmidt@linux.ibm.com>

gcc/
	PR target/95082
	* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Handle
	endianness for vclzlsbb and vctzlsbb.
	* config/rs6000/rs6000-builtins.def (VCLZLSBB_V16QI): Change
	default pattern and indicate a different pattern will be used for
	big endian.
	(VCLZLSBB_V4SI): Likewise.
	(VCLZLSBB_V8HI): Likewise.
	(VCTZLSBB_V16QI): Likewise.
	(VCTZLSBB_V4SI): Likewise.
	(VCTZLSBB_V8HI): Likewise.

gcc/testsuite/
	PR target/95082
	* gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: Restrict to -mbig.
	* gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: Likewise.
	* gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c: New.
	* gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c: New.
	* gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: Restrict to -mbig.
	* gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: Likewise.
	* gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c: New.
	* gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c: New.
---
 gcc/config/rs6000/rs6000-builtin.cc               | 12 ++++++++++++
 gcc/config/rs6000/rs6000-builtins.def             | 12 ++++++------
 .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c     |  2 +-
 .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c     |  2 +-
 .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c     | 15 +++++++++++++++
 .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c     | 15 +++++++++++++++
 .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c     |  2 +-
 .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c     |  2 +-
 .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c     | 15 +++++++++++++++
 .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c     | 15 +++++++++++++++
 10 files changed, 82 insertions(+), 10 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 6eca3568c02..421277a0ef0 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3485,6 +3485,18 @@  rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
 	icode = CODE_FOR_vsx_store_v8hi;
       else if (fcode == RS6000_BIF_ST_ELEMREV_V16QI)
 	icode = CODE_FOR_vsx_store_v16qi;
+      else if (fcode == RS6000_BIF_VCLZLSBB_V16QI)
+	icode = CODE_FOR_vclzlsbb_v16qi;
+      else if (fcode == RS6000_BIF_VCLZLSBB_V4SI)
+	icode = CODE_FOR_vclzlsbb_v4si;
+      else if (fcode == RS6000_BIF_VCLZLSBB_V8HI)
+	icode = CODE_FOR_vclzlsbb_v8hi;
+      else if (fcode == RS6000_BIF_VCTZLSBB_V16QI)
+	icode = CODE_FOR_vctzlsbb_v16qi;
+      else if (fcode == RS6000_BIF_VCTZLSBB_V4SI)
+	icode = CODE_FOR_vctzlsbb_v4si;
+      else if (fcode == RS6000_BIF_VCTZLSBB_V8HI)
+	icode = CODE_FOR_vctzlsbb_v8hi;
       else
 	gcc_unreachable ();
     }
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index cfe31c2e7de..2bb997a5279 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2551,13 +2551,13 @@ 
     VBPERMD altivec_vbpermd {}
 
   const signed int __builtin_altivec_vclzlsbb_v16qi (vsc);
-    VCLZLSBB_V16QI vclzlsbb_v16qi {}
+    VCLZLSBB_V16QI vctzlsbb_v16qi {endian}
 
   const signed int __builtin_altivec_vclzlsbb_v4si (vsi);
-    VCLZLSBB_V4SI vclzlsbb_v4si {}
+    VCLZLSBB_V4SI vctzlsbb_v4si {endian}
 
   const signed int __builtin_altivec_vclzlsbb_v8hi (vss);
-    VCLZLSBB_V8HI vclzlsbb_v8hi {}
+    VCLZLSBB_V8HI vctzlsbb_v8hi {endian}
 
   const vsc __builtin_altivec_vctzb (vsc);
     VCTZB ctzv16qi2 {}
@@ -2572,13 +2572,13 @@ 
     VCTZW ctzv4si2 {}
 
   const signed int __builtin_altivec_vctzlsbb_v16qi (vsc);
-    VCTZLSBB_V16QI vctzlsbb_v16qi {}
+    VCTZLSBB_V16QI vclzlsbb_v16qi {endian}
 
   const signed int __builtin_altivec_vctzlsbb_v4si (vsi);
-    VCTZLSBB_V4SI vctzlsbb_v4si {}
+    VCTZLSBB_V4SI vclzlsbb_v4si {endian}
 
   const signed int __builtin_altivec_vctzlsbb_v8hi (vss);
-    VCTZLSBB_V8HI vctzlsbb_v8hi {}
+    VCTZLSBB_V8HI vclzlsbb_v8hi {endian}
 
   const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc);
     VCMPAEB_P vector_ae_v16qi_p {}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c
index 0faf233425e..dc92d6fdd65 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */
 
 #include <altivec.h>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c
index 201ed17e2fd..6fefb893936 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */
 
 #include <altivec.h>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c
new file mode 100644
index 00000000000..6ee31a11aee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */
+
+#include <altivec.h>
+
+int
+count_leading_zero_byte_bits (vector signed char *arg1_p)
+{
+  vector signed char arg_1 = *arg1_p;
+
+  return vec_cntlz_lsbb (arg_1);
+}
+
+/* { dg-final { scan-assembler "vctzlsbb" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c
new file mode 100644
index 00000000000..6105091b016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */
+
+#include <altivec.h>
+
+int
+count_leading_zero_byte_bits (vector unsigned char *arg1_p)
+{
+  vector unsigned char arg_1 = *arg1_p;
+
+  return vec_cntlz_lsbb (arg_1);
+}
+
+/* { dg-final { scan-assembler "vctzlsbb" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c
index 70a398ac401..68d6c5ff4e8 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */
 
 #include <altivec.h>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c
index f6d41e3e728..f971ea0a807 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile { target { powerpc*-*-* } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */
 
 #include <altivec.h>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c
new file mode 100644
index 00000000000..a9245d8200c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */
+
+#include <altivec.h>
+
+int
+count_trailing_zero_byte_bits (vector signed char *arg1_p)
+{
+  vector signed char arg_1 = *arg1_p;
+
+  return vec_cnttz_lsbb (arg_1);
+}
+
+/* { dg-final { scan-assembler "vclzlsbb" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c
new file mode 100644
index 00000000000..71fea5306c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */
+
+#include <altivec.h>
+
+int
+count_trailing_zero_byte_bits (vector unsigned char *arg1_p)
+{
+  vector unsigned char arg_1 = *arg1_p;
+
+  return vec_cnttz_lsbb (arg_1);
+}
+
+/* { dg-final { scan-assembler "vclzlsbb" } } */