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Wed, 2 Sep 2026 05:28:29 -0500 (EST) From: Vijay Shankar To: gcc-patches@gcc.gnu.org, jskumari@linux.ibm.com, meissner@linux.ibm.com Cc: avinashd@linux.ibm.com, kishan@linux.ibm.com, jeevitha@linux.ibm.com, Vijay Shankar Subject: [PATCH v4] rs6000: Add POWER10 wide-immediate fusion patterns [PR108018] Date: Wed, 2 Sep 2026 05:28:23 -0500 Message-ID: <20260902102823.3450931-1-vijay@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: KTAERAu22rdQ-oYox_Lf9hiWdK1QpqIz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAyMDA4OCBTYWx0ZWRfXzJ73XUDAQ3zZ +NGT2j/IZytB246wevdIWnXUEwXEEPiQnTbEpGEJCoIX9PehDan0E7GnuLaQgFL6NJ9bLnfMy6V eABSqSbfOZ8ItkX6yPmPtbHoFPhHzyBdBXBskgtpTYY4e2brHZl25DxvX5y3ZgNWxXfcZa8eveL qSwn5M8ByA7JEx3p2KYRJ7ld7lqK5PCQN1M4DrHlrGBd0cW9/HXu9Z+DxQgu/zwivhkAl1NaRPl SGxj2EJr7wcuTU2nf2N6RsBrti36bERY0bzLBCXiFfWWrSRRmsL7jQikgIj4KLEVaxDqyikpfnL 8xSfWdb9HYlm4/Wn+eD8kQziyz1hxdYCYEkk0Mlu/k+HAS+aO4LaNbBuitv5ihwUHqfO1muvAFs NEHaCMbvxJnxo6ZZwKgleWfjXARsyQPrvc2bP1JHf+OM/+bPXOWd/Flf5NBQOvsTu+u4avUtULF Afjhu0+uN2cKPD+drnA== X-Proofpoint-ORIG-GUID: KTAERAu22rdQ-oYox_Lf9hiWdK1QpqIz X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAyMDA4OCBTYWx0ZWRfX+S5kbVmrZQcG LfSXAKyaO7phVM4hfljlyLcnf/u4AbQgkmcEruj1GNyx4tcJGMFkOs2undOkVrryYDtacQyGzGT 1Lg6gGvsuJe5HQgXqe17frdrfUnhC/M= X-Authority-Analysis: v=2.4 cv=B92JFutM c=1 sm=1 tr=0 ts=6a97fa4f cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=VdqzKS8jKosA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8 a=M6dRWEXpnb-jRJT9c5QA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-02_02,2026-09-01_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609020088 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_PBL, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Hello, Changes form v3: * use TARGET_P10_FUSION instead of tuning conditions * disable test for 32 bit Changes form v2: * Removed AIX related changes * update test case to check pattern directly Changes form v1: * Cleaned up naming in rs6000.md * Cleaned up guards to be on same line. * Test case use \m...\M instead of relying on space Thank you, Vijay. POWER10 has instruction fusion for addis+addi pairs. However, the scheduler was breaking these pairs apart to optimize for dependency chains, losing the fusion benefit. This patch implements "fake" instructions that represent both instructions as a single pattern. This prevents the scheduler from reordering them while still generating the correct two-instruction sequence. Existing high/low patterns are guarded to prevent conflicts with the new fusion patterns. Bootstrapped and tested on powerpc64le-linux-gnu with no regressions. Bootstrapped and tested on powerpc64-linux-gnu with no regressions. 2026-03-16 Vijay Shankar gcc/ChangeLog: PR target/108018 * config/rs6000/rs6000.md (*largetoc_high): Add guards. (*largetoc_high_plus): Likewise. (*largetoc_low): Likewise. (*largetocp10): New define_insn. (*largetocp10_plus): Likewise. (*tocref): Add guards. gcc/testsuite/ChangeLog: PR target/108018 * gcc.target/powerpc/pr108018.c: New test. --- gcc/config/rs6000/rs6000.md | 33 ++++++++++++++++++--- gcc/testsuite/gcc.target/powerpc/pr108018.c | 16 ++++++++++ 2 files changed, 45 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108018.c diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index ddfed3b63bc..8178fa5a837 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11366,7 +11366,8 @@ (unspec [(match_operand:DI 1 "" "") (match_operand:DI 2 "gpc_reg_operand" "b")] UNSPEC_TOCREL)))] - "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" + "!TARGET_P10_FUSION + && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" "addis %0,%2,%1@toc@ha") (define_insn "*largetoc_high_aix" @@ -11386,7 +11387,8 @@ (match_operand:DI 2 "gpc_reg_operand" "b")] UNSPEC_TOCREL) (match_operand:DI 3 "add_cint_operand" "n"))))] - "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" + "!TARGET_P10_FUSION + && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" "addis %0,%2,%1+%3@toc@ha") (define_insn "*largetoc_high_plus_aix" @@ -11404,7 +11406,8 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b") (match_operand:DI 2 "" "")))] - "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" + "!TARGET_P10_FUSION + && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" "addi %0,%1,%2@l") (define_insn "*largetoc_low_aix" @@ -11414,11 +11417,33 @@ "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL" "la %0,%2@l(%1)") +(define_insn "*largetocp10" + [(set (match_operand:DI 0 "gpc_reg_operand" "=b") + (unspec [(match_operand:DI 1 "" "") + (match_operand:DI 2 "gpc_reg_operand" "b")] + UNSPEC_TOCREL))] + "TARGET_P10_FUSION + && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" + "addis %0,%2,%1@toc@ha\;addi %0,%0,%1@toc@l") + +(define_insn "*largetocp10_plus" + [(set (match_operand:DI 0 "gpc_reg_operand" "=b") + (plus:DI + (unspec [(match_operand:DI 1 "" "") + (match_operand:DI 2 "gpc_reg_operand" "b")] + UNSPEC_TOCREL) + (match_operand:DI 3 "add_cint_operand" "n")))] + "TARGET_P10_FUSION + && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" + "addis %0,%2,%1+%3@toc@ha\;addi %0,%0,%1+%3@toc@l") + (define_insn_and_split "*tocref" [(set (match_operand:P 0 "gpc_reg_operand" "=b") (match_operand:P 1 "small_toc_ref" "R"))] "TARGET_TOC - && legitimate_constant_pool_address_p (operands[1], QImode, false)" + && legitimate_constant_pool_address_p (operands[1], QImode, false) + && (!TARGET_P10_FUSION + || (TARGET_P10_FUSION && TARGET_XCOFF))" "la %0,%a1" "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed" [(set (match_dup 0) (high:P (match_dup 1))) diff --git a/gcc/testsuite/gcc.target/powerpc/pr108018.c b/gcc/testsuite/gcc.target/powerpc/pr108018.c new file mode 100644 index 00000000000..cf3a59d45ba --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr108018.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { powerpc*-*-aix* } } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -dp -mcpu=power9 -mtune=power10" } */ + +/* Verify that the test case from PR108018 won't fail. */ + +static int foo, bar; + +unsigned long test(void) +{ + return (unsigned long)&foo + (unsigned long)&bar; +} + +/* { dg-final { scan-assembler {\m.*largetocp10\M} } } */ +/* { dg-final { scan-assembler {\m.*largetocp10_plus\M} } } */