diff mbox series

[v4] rs6000: Add POWER10 wide-immediate fusion patterns [PR108018]

Message ID 20260902102823.3450931-1-vijay@linux.ibm.com
State New
Headers
Series [v4] rs6000: Add POWER10 wide-immediate fusion patterns [PR108018] |

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Commit Message

Vijay shankar telidevulapalli Sept. 2, 2026, 10:28 a.m. UTC 
  Hello,
Changes form v3:
        * use TARGET_P10_FUSION instead of tuning conditions
        * disable test for 32 bit

Changes form v2:
        * Removed AIX related changes
        * update test case to check pattern directly

Changes form v1:
        * Cleaned up naming in rs6000.md
        * Cleaned up guards to be on same line.
        * Test case use \m...\M instead of relying on space

Thank you,
Vijay.

POWER10 has instruction fusion for addis+addi pairs. However,
the scheduler was breaking these pairs apart to optimize for
dependency chains, losing the fusion benefit.

This patch implements "fake" instructions that represent both
instructions as a single pattern. This prevents the scheduler from
reordering them while still generating the correct two-instruction
sequence.

Existing high/low patterns are guarded to
prevent conflicts with the new fusion patterns.

Bootstrapped and tested on powerpc64le-linux-gnu with no regressions.
Bootstrapped and tested on powerpc64-linux-gnu with no regressions.

2026-03-16  Vijay Shankar  <vijay@linux.ibm.com>

gcc/ChangeLog:
	PR target/108018
	* config/rs6000/rs6000.md (*largetoc_high): Add guards.
	(*largetoc_high_plus): Likewise.
	(*largetoc_low): Likewise.
	(*largetocp10): New define_insn.
	(*largetocp10_plus): Likewise.
	(*tocref<mode>): Add guards.

gcc/testsuite/ChangeLog:
	PR target/108018
	* gcc.target/powerpc/pr108018.c: New test.
---
 gcc/config/rs6000/rs6000.md                 | 33 ++++++++++++++++++---
 gcc/testsuite/gcc.target/powerpc/pr108018.c | 16 ++++++++++
 2 files changed, 45 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108018.c
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index ddfed3b63bc..8178fa5a837 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -11366,7 +11366,8 @@ 
 	  (unspec [(match_operand:DI 1 "" "")
 		   (match_operand:DI 2 "gpc_reg_operand" "b")]
 		  UNSPEC_TOCREL)))]
-   "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
+   "!TARGET_P10_FUSION
+    && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
    "addis %0,%2,%1@toc@ha")
 
 (define_insn "*largetoc_high_aix<mode>"
@@ -11386,7 +11387,8 @@ 
 		     (match_operand:DI 2 "gpc_reg_operand" "b")]
 		    UNSPEC_TOCREL)
 	    (match_operand:DI 3 "add_cint_operand" "n"))))]
-   "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
+   "!TARGET_P10_FUSION
+    && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
    "addis %0,%2,%1+%3@toc@ha")
 
 (define_insn "*largetoc_high_plus_aix<mode>"
@@ -11404,7 +11406,8 @@ 
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b")
 	           (match_operand:DI 2 "" "")))]
-   "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
+   "!TARGET_P10_FUSION
+    && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
    "addi %0,%1,%2@l")
 
 (define_insn "*largetoc_low_aix<mode>"
@@ -11414,11 +11417,33 @@ 
    "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
    "la %0,%2@l(%1)")
 
+(define_insn "*largetocp10"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
+	(unspec [(match_operand:DI 1 "" "")
+		 (match_operand:DI 2 "gpc_reg_operand" "b")]
+		UNSPEC_TOCREL))]
+   "TARGET_P10_FUSION
+    && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
+   "addis %0,%2,%1@toc@ha\;addi %0,%0,%1@toc@l")
+
+(define_insn "*largetocp10_plus"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
+	(plus:DI
+	  (unspec [(match_operand:DI 1 "" "")
+		   (match_operand:DI 2 "gpc_reg_operand" "b")]
+		  UNSPEC_TOCREL)
+	  (match_operand:DI 3 "add_cint_operand" "n")))]
+   "TARGET_P10_FUSION
+    && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
+   "addis %0,%2,%1+%3@toc@ha\;addi %0,%0,%1+%3@toc@l")
+
 (define_insn_and_split "*tocref<mode>"
   [(set (match_operand:P 0 "gpc_reg_operand" "=b")
 	(match_operand:P 1 "small_toc_ref" "R"))]
    "TARGET_TOC
-    && legitimate_constant_pool_address_p (operands[1], QImode, false)"
+    && legitimate_constant_pool_address_p (operands[1], QImode, false)
+    && (!TARGET_P10_FUSION
+    || (TARGET_P10_FUSION && TARGET_XCOFF))"
    "la %0,%a1"
    "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
   [(set (match_dup 0) (high:P (match_dup 1)))
diff --git a/gcc/testsuite/gcc.target/powerpc/pr108018.c b/gcc/testsuite/gcc.target/powerpc/pr108018.c
new file mode 100644
index 00000000000..cf3a59d45ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr108018.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-O2 -dp -mcpu=power9 -mtune=power10" } */
+
+/* Verify that the test case from PR108018 won't fail.  */
+
+static int foo, bar;
+
+unsigned long test(void)
+{
+        return (unsigned long)&foo + (unsigned long)&bar;
+}
+
+/* { dg-final { scan-assembler {\m.*largetocp10\M} } } */
+/* { dg-final { scan-assembler {\m.*largetocp10_plus\M} } } */