From patchwork Tue Sep 1 23:34:56 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 142665 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CA6394BA79B5 for ; Tue, 1 Sep 2026 23:36:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CA6394BA79B5 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Q0RNd5yj X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) by sourceware.org (Postfix) with ESMTPS id 5331F4BA7994 for ; Tue, 1 Sep 2026 23:36:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5331F4BA7994 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5331F4BA7994 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1788305761; cv=none; b=RiMH7OX+uJGaBAvk+TzeTblmcIh4MVOcv4lyQChXYhuc6FRxyQX/1is4aRzx5MdH77afuFIsz98DRqszaRj9UcrwScv7D27H+/vxx0L1HdLzRFTcZ+rEzcdEri/ZA/WCJXBRyWyrbq5UZFoBmR827+TFa0rScoeBIBtvZh6g8ps= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1788305761; c=relaxed/simple; bh=Lab2TU/g4/8VSTlA0glgh91x4cTGxhxnvVhGxikFeZ0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=iGTIM2OQztImQxCeBLExg64eGQNPK4fBuxWoduZJqc2pmTiwvmNo6KudAOyBPL+dZ1k9tQkbKl944d0QOk+TTAkyTwbTYQP8x957UXbVjJqgE/vli5BErU0pDc1C/+rlhdKA/y/K8rUz53HvtMQH0QfRZKpXxJB6lOA+adwZCj4= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Q0RNd5yj DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5331F4BA7994 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788305761; x=1819841761; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Lab2TU/g4/8VSTlA0glgh91x4cTGxhxnvVhGxikFeZ0=; b=Q0RNd5yjNOd1qH3f8PGyuU+oZOADf6LtbYmpceUmxh2vs7ZPFhm/Q0Vz C/edLu2lVH6uKVcQrSuO/wwbTrJCNkVodUPKeFQvtG+Xw/RYbVoHZVN+/ 7wJh2wALH0tAvo84fgQkSS6rlUUjUIBX0ShLQP59fIOZ6DRY+9k1kUUa6 J7AjFlow+xdwQpE9BluWQjTJ3j/co413yyYBhA7U6E+0lrj20BYE0bL8j KrmYJe/TYpdwjkKtqleHgvPt8cT6S+bB9m4EvZ6xEjdVJflVqmKl9ILAa OeuO/UVooiwv57aKiXV7Vn+CPsDjawtbyi8d0nG5p3gloKR2mBhcW6M9G A==; X-CSE-ConnectionGUID: 6ehj3czYSOiuNpvXQwCg8A== X-CSE-MsgGUID: 0s4DJmrVSQW89J7KBHzWZg== X-IronPort-AV: E=McAfee;i="6800,10657,11893"; a="76305057" X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="76305057" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2026 16:36:00 -0700 X-CSE-ConnectionGUID: fwXwO3XZQNWJAWGBlV/vug== X-CSE-MsgGUID: ZHQxZY8IQEG26xcAlVmL8Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,256,1779174000"; d="scan'208";a="271197210" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa004.fm.intel.com with ESMTP; 01 Sep 2026 16:35:58 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 3/3] RISC-V: Add more test cases for vwmaccus.vx Date: Wed, 2 Sep 2026 07:34:56 +0800 Message-ID: <20260901233549.3563543-4-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260901233549.3563543-1-pan2.li@intel.com> References: <20260901233549.3563543-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li For csrr not asm check when enable overlap enabled. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-57.c: New test. * gcc.target/riscv/rvv/base/pr112431-58.c: New test. Signed-off-by: Pan Li --- .../gcc.target/riscv/rvv/base/pr112431-57.c | 62 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr112431-58.c | 62 +++++++++++++++++++ 2 files changed, 124 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c new file mode 100644 index 00000000000..5c91a7b5f83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-57.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n, uint8_t x) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v0_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v0, 1)); + v0 = __riscv_vwmaccus_vx_i16m4_tu (v0, x, v0_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v1_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v1, 1)); + v1 = __riscv_vwmaccus_vx_i16m4_tu (v1, x, v1_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v2_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v2, 1)); + v2 = __riscv_vwmaccus_vx_i16m4_tu (v2, x, v2_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v3_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v3, 1)); + v3 = __riscv_vwmaccus_vx_i16m4_tu (v3, x, v3_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v4_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v4, 1)); + v4 = __riscv_vwmaccus_vx_i16m4_tu (v4, x, v4_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v5_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v5, 1)); + v5 = __riscv_vwmaccus_vx_i16m4_tu (v5, x, v5_n, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v6 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v6_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v6, 1)); + v6 = __riscv_vwmaccus_vx_i16m4_tu (v6, x, v6_n, 4); + asm volatile("nop" ::: "memory"); + vint8m2_t v7_n = __riscv_vle8_v_i8m2 (in, 4);in+=100; + vint16m4_t v7 = __riscv_vwcvt_x_x_v_i16m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v7, 4);out+=100; + } +} + +/* The narrowed signed source is the highest-numbered half of the signed + accumulator, thus it overlaps the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c new file mode 100644 index 00000000000..a6da2bc4009 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-58.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n, uint16_t x) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vint32m4_t v0 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v0_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v0, 1)); + v0 = __riscv_vwmaccus_vx_i32m4_tu (v0, x, v0_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v1 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v1_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v1, 1)); + v1 = __riscv_vwmaccus_vx_i32m4_tu (v1, x, v1_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v2 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v2_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v2, 1)); + v2 = __riscv_vwmaccus_vx_i32m4_tu (v2, x, v2_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v3 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v3_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v3, 1)); + v3 = __riscv_vwmaccus_vx_i32m4_tu (v3, x, v3_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v4 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v4_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v4, 1)); + v4 = __riscv_vwmaccus_vx_i32m4_tu (v4, x, v4_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v5 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v5_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v5, 1)); + v5 = __riscv_vwmaccus_vx_i32m4_tu (v5, x, v5_n, 4); + asm volatile("nop" ::: "memory"); + vint32m4_t v6 = __riscv_vle32_v_i32m4 (in, 4);in+=100; + vint16m2_t v6_n = __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vget_v_i32m4_i32m2 (v6, 1)); + v6 = __riscv_vwmaccus_vx_i32m4_tu (v6, x, v6_n, 4); + asm volatile("nop" ::: "memory"); + vint16m2_t v7_n = __riscv_vle16_v_i16m2 (in, 4);in+=100; + vint32m4_t v7 = __riscv_vwcvt_x_x_v_i32m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse32_v_i32m4 (out, 4, v0, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v1, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v2, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v3, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v4, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v5, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v6, 4);out+=100; + __riscv_vsse32_v_i32m4 (out, 4, v7, 4);out+=100; + } +} + +/* The narrowed signed source is the highest-numbered half of the signed + accumulator, thus it overlaps the destination register group. */ +/* { dg-final { scan-assembler-times {vwmaccus\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */