From patchwork Wed Aug 5 08:00:45 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 140629 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 13CA84BAE7D2 for ; Wed, 5 Aug 2026 08:05:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 13CA84BAE7D2 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=T/T2iTJV X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by sourceware.org (Postfix) with ESMTPS id CE5934BA7986 for ; Wed, 5 Aug 2026 08:02:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CE5934BA7986 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CE5934BA7986 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1785916935; cv=none; b=GKZceY/5hlbLuMGyofmUmqiMDa7iHdquawDORjQM05c24R/4eb0ORvufuRkqnzEjhkFWsxp2hFGgfgyxYcDh1yWJ2Z6TORttRGA1o2/ysNUt0ATcemKKf003FE/xGOuKJIHyj+vZhBpH7X0oO+kuF/r6gCXCTEZry2DfT01rIxI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1785916935; c=relaxed/simple; bh=zAbgmWEMn7KJKJogrABzsXb52jj6JCqQ9ZTpRh7Ac40=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=pCIXw2sjWCPNIFWSBvQ75tFTHlFtW7b9RDO5NB02IQ4nNOAf59Ms+etcGkcYUuXrnvLusKtXcAroMznxb5jet10YgzpwvjSfbrVVjvLxzFqq2P4jo9ZpPx1fyLlAE4pcNJ+FtsjB1Ux65F926SQbVDtRRbdfQbm/2m9Bifshb6w= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=T/T2iTJV DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CE5934BA7986 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785916935; x=1817452935; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zAbgmWEMn7KJKJogrABzsXb52jj6JCqQ9ZTpRh7Ac40=; b=T/T2iTJV7/Rx18BFre3GltHrROQDVzqIIf06gO1H9icuD1EcfNhWF3Fj EvCGkJVWbyC5/WdZ79Z4ZsYSxe6PPamkBpSH+CZ4mgzIIRYBf/eiW3SpA rK2m9NbFbg0QVDMnM7tuK/uQifnGUVcVxf9VbRDC3IHAEZPMY+gxokToC Jr20NQIIjUuMneOqRnMCOi4pb/sRBj6IqlLq6r9Mimel6eSREooxnd3hE +pm10wkoMURCb5nTaIincuz1WEAX+TQ64hzEtqJdTwIGDwwPY3yz3Zi7C +zWDyxzTGb2xxmpmSpu0NSDEwPTXYUkRzm3EkjAGHrJ9S7Ui7ZLavfKj5 g==; X-CSE-ConnectionGUID: 3MTC//ghSY6xiHHB2i1kmQ== X-CSE-MsgGUID: x9aNveTIR9SSzqEsAnIO3A== X-IronPort-AV: E=McAfee;i="6800,10657,11865"; a="90297845" X-IronPort-AV: E=Sophos;i="6.25,206,1779174000"; d="scan'208";a="90297845" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2026 01:02:08 -0700 X-CSE-ConnectionGUID: XTgNF6ljS+Grwd98NMTiZg== X-CSE-MsgGUID: BZgAt8sZSbKvMNE5fMS/Wg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,206,1779174000"; d="scan'208";a="258396144" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa007.fm.intel.com with ESMTP; 05 Aug 2026 01:01:54 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li , Claude Opus 5 Subject: [PATCH v1 3/3] RISC-V: Add more test cases for vwmulsu.vv Date: Wed, 5 Aug 2026 16:00:45 +0800 Message-ID: <20260805080146.2333958-4-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805080146.2333958-1-pan2.li@intel.com> References: <20260805080146.2333958-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li For csrr not asm check when enable overlap enabled. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-48.c: New test. Signed-off-by: Pan Li Co-Authored-By: Claude Opus 5 (1M context) --- .../gcc.target/riscv/rvv/base/pr112431-48.c | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c new file mode 100644 index 00000000000..17631c347b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v0_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v0, 1)); + vuint8m2_t v0_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v0_n); + v0 = __riscv_vwmulsu_vv_i16m4_tu (v0, v0_n, v0_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v1_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v1, 1)); + vuint8m2_t v1_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v1_n); + v1 = __riscv_vwmulsu_vv_i16m4_tu (v1, v1_n, v1_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v2_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v2, 1)); + vuint8m2_t v2_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v2_n); + v2 = __riscv_vwmulsu_vv_i16m4_tu (v2, v2_n, v2_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v3_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v3, 1)); + vuint8m2_t v3_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v3_n); + v3 = __riscv_vwmulsu_vv_i16m4_tu (v3, v3_n, v3_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v4_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v4, 1)); + vuint8m2_t v4_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v4_n); + v4 = __riscv_vwmulsu_vv_i16m4_tu (v4, v4_n, v4_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v5_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v5, 1)); + vuint8m2_t v5_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v5_n); + v5 = __riscv_vwmulsu_vv_i16m4_tu (v5, v5_n, v5_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v6 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v6_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v6, 1)); + vuint8m2_t v6_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v6_n); + v6 = __riscv_vwmulsu_vv_i16m4_tu (v6, v6_n, v6_nu, 4); + asm volatile("nop" ::: "memory"); + vint8m2_t v7_n = __riscv_vle8_v_i8m2 (in, 4);in+=100; + vint16m4_t v7 = __riscv_vwcvt_x_x_v_i16m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v7, 4);out+=100; + } +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */