From patchwork Wed Aug 5 08:00:43 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 140626 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CFE424BA2E23 for ; Wed, 5 Aug 2026 08:03:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CFE424BA2E23 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=HqDp/QVR X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by sourceware.org (Postfix) with ESMTPS id 8C8A64BA2E08 for ; Wed, 5 Aug 2026 08:02:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8C8A64BA2E08 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8C8A64BA2E08 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1785916932; cv=none; b=osw5Rl9pKsa9uCPJ4LeMEYB1l6hnrD+47RlTfWAYqOKHzb7mnIiTSI3D6WUmhCZRceopUSBKyp7UULLNJrbTtEKUcEnBBNMTcaxnkgBGFhEq0zuvM7+ED/JG2QXglAQCwpMlJMymvaLoGiMh24kekJHvSzI+R4NolvgOjSFuhaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1785916932; c=relaxed/simple; bh=9TNiSegsHXmaSlNxL58RPPcZfAEldUkMoQvEgapqrbw=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Uvqe4SAWbONrILr8EOHtvLnX/E3wViSGdmXl92O+MZioN4bE7uWAA89ZiBDxurUWPMiPTS2djjehTyoBiwQFmBORK5zB+xwnrFCqvJ3O99s0/pdXptio6BXPy8SytmsX1C4EDhO1m9F4lX+/kVNEsazOdPx2TvrW8SsPeYJ7lHo= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=HqDp/QVR DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8C8A64BA2E08 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785916932; x=1817452932; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9TNiSegsHXmaSlNxL58RPPcZfAEldUkMoQvEgapqrbw=; b=HqDp/QVRQKkccX2uGxO5qyz6PrgsWzECCI8Ce6moEXQqOQng1gJ2yVxD XiFQniZWit+hHdoGsHY+hJoCY63LaH1DqrqM8HerBkWcfLDDbHNPYefr6 YBDhx9YgDlyzQpkndt7bxSWaY5SN5WmrnhLa9vjD0lR5Ae2OwS0jk9q6I YpTvKm4Q7OSvIXkRlvDH3DUec8UMlwvRRFFjCUcoR1BEDTBxJNCwXVhq2 MY1NUqGrTPJm7Y/A8QkyLHsDcBs53WoKa+WQ3HxIyOkI+trfMi7XWD/vj YzgX6dR1N/fyl+cXfaKiuKYKFh7cQG5LRS0CPEnHPyw+1W1QuEwYwK9HV A==; X-CSE-ConnectionGUID: ZYwMMqRZQdW7QxHsYCtngQ== X-CSE-MsgGUID: 8OL/QgocRM+9VVpSvlimYQ== X-IronPort-AV: E=McAfee;i="6800,10657,11865"; a="90297835" X-IronPort-AV: E=Sophos;i="6.25,206,1779174000"; d="scan'208";a="90297835" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2026 01:02:07 -0700 X-CSE-ConnectionGUID: PKlmghDtRCOBZG0owDa4Gg== X-CSE-MsgGUID: EwOoEZjsRIu5IdlfIjxmhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,206,1779174000"; d="scan'208";a="258396140" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa007.fm.intel.com with ESMTP; 05 Aug 2026 01:01:49 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li , Claude Opus 5 Subject: [PATCH v1 1/3] RISC-V: Allow RVV register overlap for vwmulsu.vv Date: Wed, 5 Aug 2026 16:00:43 +0800 Message-ID: <20260805080146.2333958-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805080146.2333958-1-pan2.li@intel.com> References: <20260805080146.2333958-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Like vw{add,sub,mul}[u].vv, allow the rvv register overlap for the dual widen vv insn vwmulsu.vv. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li Co-Authored-By: Claude Opus 5 (1M context) --- gcc/config/riscv/vector.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index afaa3a51ece..4efee02fb3b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4303,22 +4303,22 @@ (define_insn "@pred_single_widen_sub_extended_scalar" (set_attr "mode" "")]) (define_insn "@pred_widen_mulsu" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vd, vd") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rvl, rvl") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "Wc1,Wc1, vm, vm") + (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (mult:VWEXTI (sign_extend:VWEXTI - (match_operand: 3 "register_operand" " vr, vr")) + (match_operand: 3 "register_operand" "Wvr,Wvr,Wvr,Wvr")) (zero_extend:VWEXTI - (match_operand: 4 "register_operand" " vr, vr"))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 4 "register_operand" "Wvr,Wvr,Wvr,Wvr"))) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vwmulsu.vv\t%0,%3,%4%p1" [(set_attr "type" "viwmul")