diff mbox series

[v1,1/3] RISC-V: Allow RVV register overlap for vwmulsu.vv

Message ID 20260805080146.2333958-2-pan2.li@intel.com
State New
Headers
Series Support RVV register overlap for vwmulsu.vv |

Commit Message

Li, Pan2 Aug. 5, 2026, 8 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Like vw{add,sub,mul}[u].vv, allow the rvv register overlap for
the dual widen vv insn vwmulsu.vv.

gcc/ChangeLog:

	* config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
---
 gcc/config/riscv/vector.md | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

Comments

Robin Dapp Aug. 5, 2026, 2:50 p.m. UTC | #1 
> Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

I hope/guess you just default-added this to all of your messages?
While assisted-by/co-authored-by would be OK for a testsuite change, it 
generally isn't for regular code.  While this is of course a carbon copy 
of all the related changes, it's not a direct refactoring either and 
IMHO it's at least ambiguous.  I'm not very happy having to play 
"copyright lawyer" now... but I think this is still fine.

Legal insignificance is an exception to the general policy that 
LLM-assisted code is not OK.

So this is OK but instead of just adding the tag, in the future please 
also state why you think the particular assisted-by change is legally 
insignificant.  Otherwise we cannot ACK it.
Li, Pan2 Aug. 6, 2026, 12:30 a.m. UTC | #2 
I see, thanks Robin.

Only the test cases are LLM-assisted, but it will add that tag automatically when you ask help from LLM.
I will make it clear before commit, as well as the underlying patches.

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Wednesday, August 5, 2026 10:51 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@gmail.com; jeffreyalaw@gmail.com; rdapp.gcc@gmail.com; Chen, Ken <ken.chen@intel.com>; Liu, Hongtao <hongtao.liu@intel.com>
Subject: Re: [PATCH v1 1/3] RISC-V: Allow RVV register overlap for vwmulsu.vv

> Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

I hope/guess you just default-added this to all of your messages?
While assisted-by/co-authored-by would be OK for a testsuite change, it 
generally isn't for regular code.  While this is of course a carbon copy 
of all the related changes, it's not a direct refactoring either and 
IMHO it's at least ambiguous.  I'm not very happy having to play 
"copyright lawyer" now... but I think this is still fine.

Legal insignificance is an exception to the general policy that 
LLM-assisted code is not OK.

So this is OK but instead of just adding the tag, in the future please 
also state why you think the particular assisted-by change is legally 
insignificant.  Otherwise we cannot ACK it.

-- 
Regards
 Robin
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index afaa3a51ece..4efee02fb3b 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4303,22 +4303,22 @@  (define_insn "@pred_single_widen_sub<any_extend:su><mode>_extended_scalar"
    (set_attr "mode" "<V_DOUBLE_TRUNC>")])
 
 (define_insn "@pred_widen_mulsu<mode>"
-  [(set (match_operand:VWEXTI 0 "register_operand"                  "=&vr,&vr")
+  [(set (match_operand:VWEXTI 0 "register_operand"                 "=vr, vr, vd, vd")
 	(if_then_else:VWEXTI
 	  (unspec:<VM>
-	    [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
-	     (match_operand 5 "vector_length_operand"              "  rvl,  rvl")
-	     (match_operand 6 "const_int_operand"                  "    i,    i")
-	     (match_operand 7 "const_int_operand"                  "    i,    i")
-	     (match_operand 8 "const_int_operand"                  "    i,    i")
+	    [(match_operand:<VM> 1 "vector_mask_operand"           "Wc1,Wc1, vm, vm")
+	     (match_operand 5 "vector_length_operand"              "rvl,rvl,rvl,rvl")
+	     (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
+	     (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
+	     (match_operand 8 "const_int_operand"                  "  i,  i,  i,  i")
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	  (mult:VWEXTI
 	    (sign_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   vr"))
+	      (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "Wvr,Wvr,Wvr,Wvr"))
 	    (zero_extend:VWEXTI
-	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   vr")))
-	  (match_operand:VWEXTI 2 "vector_merge_operand"           "   vu,    0")))]
+	      (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr,Wvr,Wvr")))
+	  (match_operand:VWEXTI 2 "vector_merge_operand"           " vu,  0, vu,  0")))]
   "TARGET_VECTOR"
   "vwmulsu.vv\t%0,%3,%4%p1"
   [(set_attr "type" "viwmul")