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[6/9] RISC-V: Add minimal Smsdid extension support

Message ID 20260717151506.110501-7-jiawei@iscas.ac.cn
State Deferred
Delegated to: Jeff Law
Headers
Series RISC-V: Add minimal support for Ziccid, Ziccamoc, Ssccfg, Smcdeleg, Smctr, Smsdid, Ssctr, Ssqosid and Svrsw60t59b extensions |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 fail Patch failed to apply
linaro-tcwg-bot/tcwg_simplebootstrap_build--master-aarch64-bootstrap fail Patch failed to apply

Commit Message

Jiawei July 17, 2026, 3:15 p.m. UTC 
  This adds minimal support for the Smsdid[1] (Machine-mode supervisor domain
ID) extension, which depends on Zicsr.

[1] https://github.com/riscv/riscv-smmtt

gcc/ChangeLog:

	* config/riscv/riscv-ext.def (smsdid): Add new extension.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/smsdid-version.c: New test.

---
 gcc/config/riscv/riscv-ext.def                  | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                  |  2 ++
 gcc/doc/riscv-ext.texi                          |  4 ++++
 gcc/testsuite/gcc.target/riscv/smsdid-version.c | 15 +++++++++++++++
 4 files changed, 34 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/smsdid-version.c

Comments

Jeffrey Law July 19, 2026, 3:25 a.m. UTC | #1 
On 7/17/2026 9:15 AM, Jiawei wrote:
> This adds minimal support for the Smsdid[1] (Machine-mode supervisor domain
> ID) extension, which depends on Zicsr.
>
> [1] https://github.com/riscv/riscv-smmtt
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-ext.def (smsdid): Add new extension.
> 	* config/riscv/riscv-ext.opt: Ditto.
> 	* doc/riscv-ext.texi: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/smsdid-version.c: New test.
I don't think this has hit the frozen state yet.  So I think this needs 
to wait.

jeff
Jiawei July 19, 2026, 2:31 p.m. UTC | #2 
On 2026/7/19 11:25, Jeffrey Law wrote:
>
>
> On 7/17/2026 9:15 AM, Jiawei wrote:
>> This adds minimal support for the Smsdid[1] (Machine-mode supervisor 
>> domain
>> ID) extension, which depends on Zicsr.
>>
>> [1] https://github.com/riscv/riscv-smmtt
>>
>> gcc/ChangeLog:
>>
>>     * config/riscv/riscv-ext.def (smsdid): Add new extension.
>>     * config/riscv/riscv-ext.opt: Ditto.
>>     * doc/riscv-ext.texi: Ditto.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/smsdid-version.c: New test.
> I don't think this has hit the frozen state yet.  So I think this 
> needs to wait.
>
> jeff 
I apologize for confusing the current status of Smmtt. It has entered 
the freeze
phase but has not been officially forzen, I confused them. I will 
suspend this patch.

https://riscv.atlassian.net/jira/software/c/projects/RVS/list?jql=project%20%3D%20RVS%20AND%20textfields%20~%20%22smmtt*%22%20ORDER%20BY%20cf%5B10019%5D%20ASC


Thank you for your careful review again.

Regards,
Jiawei
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 449f98a29c5..ddcd8ae1620 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1858,6 +1858,19 @@  DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ smsdid,
+  /* UPPERCASE_NAME */ SMSDID,
+  /* FULL_NAME */ "Machine-mode supervisor domain ID extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sm,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ smstateen,
   /* UPPERCASE_NAME */ SMSTATEEN,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index c25a65a1d60..fef5fe1d867 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -375,6 +375,8 @@  Mask(SMNPM) Var(riscv_sm_subext)
 
 Mask(SMRNMI) Var(riscv_sm_subext)
 
+Mask(SMSDID) Var(riscv_sm_subext)
+
 Mask(SMSTATEEN) Var(riscv_sm_subext)
 
 Mask(SMDBLTRP) Var(riscv_sm_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 14d8b928daa..2e2a6619579 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -550,6 +550,10 @@ 
 @tab 1.0
 @tab Resumable non-maskable interrupts
 
+@item @samp{smsdid}
+@tab 1.0
+@tab Machine-mode supervisor domain ID extension
+
 @item @samp{smstateen}
 @tab 1.0
 @tab State enable extension
diff --git a/gcc/testsuite/gcc.target/riscv/smsdid-version.c b/gcc/testsuite/gcc.target/riscv/smsdid-version.c
new file mode 100644
index 00000000000..bcb0dbdf7c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/smsdid-version.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_smsdid1p0 -mabi=lp64" { target { rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_smsdid1p0 -mabi=ilp32" { target { rv32 } } } */
+
+#ifndef __riscv_smsdid
+#error "Feature macro for 'smsdid' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, .*smsdid1p0" } } */