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[5/9] RISC-V: Add minimal Smctr extension support

Message ID 20260717151506.110501-6-jiawei@iscas.ac.cn
State Committed
Delegated to: Jeff Law
Headers
Series RISC-V: Add minimal support for Ziccid, Ziccamoc, Ssccfg, Smcdeleg, Smctr, Smsdid, Ssctr, Ssqosid and Svrsw60t59b extensions |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 fail Patch failed to apply

Commit Message

Jiawei July 17, 2026, 3:15 p.m. UTC 
  This adds minimal support for the Smctr[1] (Machine-mode control transfer
records) extension, which depends on Zicsr.

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv/smctr.adoc

gcc/ChangeLog:

	* config/riscv/riscv-ext.def (smctr): Add new extension.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/smctr-version.c: New test.

---
 gcc/config/riscv/riscv-ext.def                 | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                 |  2 ++
 gcc/doc/riscv-ext.texi                         |  4 ++++
 gcc/testsuite/gcc.target/riscv/smctr-version.c | 15 +++++++++++++++
 4 files changed, 34 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/smctr-version.c

Comments

Jeffrey Law July 19, 2026, 2:24 a.m. UTC | #1 
On 7/17/2026 9:15 AM, Jiawei wrote:
> This adds minimal support for the Smctr[1] (Machine-mode control transfer
> records) extension, which depends on Zicsr.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv/smctr.adoc
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-ext.def (smctr): Add new extension.
> 	* config/riscv/riscv-ext.opt: Ditto.
> 	* doc/riscv-ext.texi: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/smctr-version.c: New test.
OK with the same comments WRT URL/DESC.
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 4159be567d2..449f98a29c5 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1780,6 +1780,19 @@  DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ smctr,
+  /* UPPERCASE_NAME */ SMCTR,
+  /* FULL_NAME */ "Machine-mode control transfer records extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sm,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ smcsrind,
   /* UPPERCASE_NAME */ SMCSRIND,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index cfee9551126..c25a65a1d60 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -363,6 +363,8 @@  Mask(SMCDELEG) Var(riscv_sm_subext)
 
 Mask(SMCNTRPMF) Var(riscv_sm_subext)
 
+Mask(SMCTR) Var(riscv_sm_subext)
+
 Mask(SMCSRIND) Var(riscv_sm_subext)
 
 Mask(SMEPMP) Var(riscv_sm_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index d71ff736bef..14d8b928daa 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -526,6 +526,10 @@ 
 @tab 1.0
 @tab Cycle and instret privilege mode filtering
 
+@item @samp{smctr}
+@tab 1.0
+@tab Machine-mode control transfer records extension
+
 @item @samp{smcsrind}
 @tab 1.0
 @tab Machine-level indirect CSR access
diff --git a/gcc/testsuite/gcc.target/riscv/smctr-version.c b/gcc/testsuite/gcc.target/riscv/smctr-version.c
new file mode 100644
index 00000000000..8e2852225ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/smctr-version.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_smctr1p0 -mabi=lp64" { target { rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_smctr1p0 -mabi=ilp32" { target { rv32 } } } */
+
+#ifndef __riscv_smctr
+#error "Feature macro for 'smctr' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, .*smctr1p0" } } */