diff mbox series

[2/9] RISC-V: Add minimal Ziccamoc extension support

Message ID 20260717151506.110501-3-jiawei@iscas.ac.cn
State Committed
Delegated to: Jeff Law
Headers
Series RISC-V: Add minimal support for Ziccid, Ziccamoc, Ssccfg, Smcdeleg, Smctr, Smsdid, Ssctr, Ssqosid and Svrsw60t59b extensions |

Commit Message

Jiawei July 17, 2026, 3:14 p.m. UTC 
  This adds minimal support for the Ziccamoc[1] (Main memory supports
compare-and-swap atomics) extension.

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/ziccamoc.adoc

gcc/ChangeLog:

	* config/riscv/riscv-ext.def (ziccamoc): Add new extension.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/ziccamoc-version.c: New test.

---
 gcc/config/riscv/riscv-ext.def                    | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                    |  2 ++
 gcc/doc/riscv-ext.texi                            |  4 ++++
 gcc/testsuite/gcc.target/riscv/ziccamoc-version.c | 15 +++++++++++++++
 4 files changed, 34 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/ziccamoc-version.c

Comments

Jeffrey Law July 18, 2026, 11:55 p.m. UTC | #1 
On 7/17/2026 9:14 AM, Jiawei wrote:
> This adds minimal support for the Ziccamoc[1] (Main memory supports
> compare-and-swap atomics) extension.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/ziccamoc.adoc
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-ext.def (ziccamoc): Add new extension.
> 	* config/riscv/riscv-ext.opt: Ditto.
> 	* doc/riscv-ext.texi: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/ziccamoc-version.c: New test.
OK as well.  As with the prior patch, consider filling in DESC/URL, but 
it's not required.

jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index f3c7df67643..e84ef896a8d 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -285,6 +285,19 @@  DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ ziccamoc,
+  /* UPPERCASE_NAME */ ZICCAMOC,
+  /* FULL_NAME */ "Main memory supports compare-and-swap atomics",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ zi,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ ziccid,
   /* UPPERCASE_NAME */ ZICCID,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 77572cec189..d70fae0c1e3 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -139,6 +139,8 @@  Mask(ZICBOZ) Var(riscv_zi_subext)
 
 Mask(ZICCAMOA) Var(riscv_zi_subext)
 
+Mask(ZICCAMOC) Var(riscv_zi_subext)
+
 Mask(ZICCID) Var(riscv_zi_subext)
 
 Mask(ZICCIF) Var(riscv_zi_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 699e5bc4d3a..b7f7982aa13 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -78,6 +78,10 @@ 
 @tab 1.0
 @tab Main memory supports all atomics in A
 
+@item @samp{ziccamoc}
+@tab 1.0
+@tab Main memory supports compare-and-swap atomics
+
 @item @samp{ziccid}
 @tab 1.0
 @tab Instruction/data coherence and consistency extension
diff --git a/gcc/testsuite/gcc.target/riscv/ziccamoc-version.c b/gcc/testsuite/gcc.target/riscv/ziccamoc-version.c
new file mode 100644
index 00000000000..c4b8f335cbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/ziccamoc-version.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_ziccamoc1p0 -mabi=lp64" { target { rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_ziccamoc1p0 -mabi=ilp32" { target { rv32 } } } */
+
+#ifndef __riscv_ziccamoc
+#error "Feature macro for 'ziccamoc' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, .*ziccamoc1p0" } } */