diff mbox series

[1/9] RISC-V: Add minimal Ziccid extension support

Message ID 20260717151506.110501-2-jiawei@iscas.ac.cn
State Committed
Delegated to: Jeff Law
Headers
Series RISC-V: Add minimal support for Ziccid, Ziccamoc, Ssccfg, Smcdeleg, Smctr, Smsdid, Ssctr, Ssqosid and Svrsw60t59b extensions |

Commit Message

Jiawei July 17, 2026, 3:14 p.m. UTC 
  This adds minimal support for the Ziccid[1] (Instruction/data coherence
and consistency) extension, which depends on Ziccif.

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/ziccid.adoc

gcc/ChangeLog:

	* config/riscv/riscv-ext.def (ziccid): Add new extension.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zi-ext.c: Add ziccid to arch test.
	* gcc.target/riscv/ziccid-version.c: New test.
	* gcc.target/riscv/ziccid.c: New test.

---
 gcc/config/riscv/riscv-ext.def                | 13 ++++++++++++
 gcc/config/riscv/riscv-ext.opt                |  2 ++
 gcc/doc/riscv-ext.texi                        |  4 ++++
 gcc/testsuite/gcc.target/riscv/zi-ext.c       |  8 ++++++--
 .../gcc.target/riscv/ziccid-version.c         | 20 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/ziccid.c       | 20 +++++++++++++++++++
 6 files changed, 65 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/ziccid-version.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/ziccid.c

Comments

Jeffrey Law July 18, 2026, 11:54 p.m. UTC | #1 
On 7/17/2026 9:14 AM, Jiawei wrote:
> This adds minimal support for the Ziccid[1] (Instruction/data coherence
> and consistency) extension, which depends on Ziccif.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/ziccid.adoc
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-ext.def (ziccid): Add new extension.
> 	* config/riscv/riscv-ext.opt: Ditto.
> 	* doc/riscv-ext.texi: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/zi-ext.c: Add ziccid to arch test.
> 	* gcc.target/riscv/ziccid-version.c: New test.
> 	* gcc.target/riscv/ziccid.c: New test.
>
>
>   
> +DEFINE_RISCV_EXT(
> +  /* NAME */ ziccid,
> +  /* UPPERCASE_NAME */ ZICCID,
> +  /* FULL_NAME */ "Instruction/data coherence and consistency extension",
> +  /* DESC */ "",
> +  /* URL */ ,
Consider entries for DESC and URL.  Not strictly necessary though. If 
you want to add them, go ahead and do so, you don't need another review 
for that.

OK for the trunk with or without DESC/URL filled in.

jeff
Jiawei July 19, 2026, 2:17 p.m. UTC | #2 
On 2026/7/19 7:54, Jeffrey Law wrote:
>
>
> On 7/17/2026 9:14 AM, Jiawei wrote:
>> This adds minimal support for the Ziccid[1] (Instruction/data coherence
>> and consistency) extension, which depends on Ziccif.
>>
>> [1] 
>> https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/ziccid.adoc
>>
>> gcc/ChangeLog:
>>
>>     * config/riscv/riscv-ext.def (ziccid): Add new extension.
>>     * config/riscv/riscv-ext.opt: Ditto.
>>     * doc/riscv-ext.texi: Ditto.
>>
>> gcc/testsuite/ChangeLog:
>>
>>     * gcc.target/riscv/zi-ext.c: Add ziccid to arch test.
>>     * gcc.target/riscv/ziccid-version.c: New test.
>>     * gcc.target/riscv/ziccid.c: New test.
>>
>>
>>   +DEFINE_RISCV_EXT(
>> +  /* NAME */ ziccid,
>> +  /* UPPERCASE_NAME */ ZICCID,
>> +  /* FULL_NAME */ "Instruction/data coherence and consistency 
>> extension",
>> +  /* DESC */ "",
>> +  /* URL */ ,
> Consider entries for DESC and URL.  Not strictly necessary though. If 
> you want to add them, go ahead and do so, you don't need another 
> review for that.
>
> OK for the trunk with or without DESC/URL filled in.
>
> jeff

Thank you for the review and comment Jeff, I will update the URL for 
currently defined RISC-V extensions with a new patch.

Best regards,
Jiawei
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 25f7f29d470..f3c7df67643 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -285,6 +285,19 @@  DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ ziccid,
+  /* UPPERCASE_NAME */ ZICCID,
+  /* FULL_NAME */ "Instruction/data coherence and consistency extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"ziccif"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ zi,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ ziccif,
   /* UPPERCASE_NAME */ ZICCIF,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 843b95fc35b..77572cec189 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -139,6 +139,8 @@  Mask(ZICBOZ) Var(riscv_zi_subext)
 
 Mask(ZICCAMOA) Var(riscv_zi_subext)
 
+Mask(ZICCID) Var(riscv_zi_subext)
+
 Mask(ZICCIF) Var(riscv_zi_subext)
 
 Mask(ZICCLSM) Var(riscv_zi_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 41614790ab8..699e5bc4d3a 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -78,6 +78,10 @@ 
 @tab 1.0
 @tab Main memory supports all atomics in A
 
+@item @samp{ziccid}
+@tab 1.0
+@tab Instruction/data coherence and consistency extension
+
 @item @samp{ziccif}
 @tab 1.0
 @tab Main memory supports instruction fetch with atomicity requirement
diff --git a/gcc/testsuite/gcc.target/riscv/zi-ext.c b/gcc/testsuite/gcc.target/riscv/zi-ext.c
index bfad74f7717..980c0179b75 100644
--- a/gcc/testsuite/gcc.target/riscv/zi-ext.c
+++ b/gcc/testsuite/gcc.target/riscv/zi-ext.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile { target { ! riscv_abi_e } } } */
-/* { dg-options "-march=rv64gc_zic64b_ziccamoa_ziccif_zicclsm_ziccrse" { target { rv64 } } } */
-/* { dg-options "-march=rv32gc_zic64b_ziccamoa_ziccif_zicclsm_ziccrse" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zic64b_ziccamoa_ziccid_ziccif_zicclsm_ziccrse" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zic64b_ziccamoa_ziccid_ziccif_zicclsm_ziccrse" { target { rv32 } } } */
 
 #ifndef __riscv_zic64b
 #error "Feature macro for 'zic64b' not defined"
@@ -10,6 +10,10 @@ 
 #error "Feature macro for 'ziccamoa' not defined"
 #endif
 
+#ifndef __riscv_ziccid
+#error "Feature macro for 'ziccid' not defined"
+#endif
+
 #ifndef __riscv_ziccif
 #error "Feature macro for 'ziccif' not defined"
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/ziccid-version.c b/gcc/testsuite/gcc.target/riscv/ziccid-version.c
new file mode 100644
index 00000000000..1aeefa91213
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/ziccid-version.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile { target { ! riscv_abi_e } } } */
+/* { dg-options "-mriscv-attribute -march=rv64i_ziccid1p0 -mabi=lp64" { target { rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_ziccid1p0 -mabi=ilp32" { target { rv32 } } } */
+
+#ifndef __riscv_ziccid
+#error "Feature macro for 'ziccid' not defined"
+#endif
+
+#ifndef __riscv_ziccif
+#error "Feature macro for 'ziccif' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_ziccid1p0_ziccif1p0\"" { target { rv64 } } } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_ziccid1p0_ziccif1p0\"" { target { rv32 } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/ziccid.c b/gcc/testsuite/gcc.target/riscv/ziccid.c
new file mode 100644
index 00000000000..5c2dde7868d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/ziccid.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile { target { ! riscv_abi_e } } } */
+/* { dg-options "-mriscv-attribute -march=rv64i_ziccid -mabi=lp64" { target { rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_ziccid -mabi=ilp32" { target { rv32 } } } */
+
+#ifndef __riscv_ziccid
+#error "Feature macro for 'ziccid' not defined"
+#endif
+
+#ifndef __riscv_ziccif
+#error "Feature macro for 'ziccif' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_ziccid1p0_ziccif1p0\"" { target { rv64 } } } } */
+/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_ziccid1p0_ziccif1p0\"" { target { rv32 } } } } */