diff mbox series

[9/9] RISC-V: Add minimal Svrsw60t59b extension support

Message ID 20260717151506.110501-10-jiawei@iscas.ac.cn
State Committed
Delegated to: Jeff Law
Headers
Series RISC-V: Add minimal support for Ziccid, Ziccamoc, Ssccfg, Smcdeleg, Smctr, Smsdid, Ssctr, Ssqosid and Svrsw60t59b extensions |

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Commit Message

Jiawei July 17, 2026, 3:15 p.m. UTC 
  This adds minimal support for the Svrsw60t59b[1] (Page-table reserved-for-
software bits 60-59) extension, and it will be a new part of RVA23.1[2].

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv/svrsw60t59b.adoc
[2] https://github.com/riscv/riscv-isa-manual/pull/3170

gcc/ChangeLog:

	* config/riscv/riscv-ext.def (svrsw60t59b): Add new extension.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/svrsw60t59b-version.c: New test.

---
 gcc/config/riscv/riscv-ext.def                    | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                    |  2 ++
 gcc/doc/riscv-ext.texi                            |  4 ++++
 .../gcc.target/riscv/svrsw60t59b-version.c        | 15 +++++++++++++++
 4 files changed, 34 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/svrsw60t59b-version.c

Comments

Jeffrey Law July 19, 2026, 3:27 a.m. UTC | #1 
On 7/17/2026 9:15 AM, Jiawei wrote:
> This adds minimal support for the Svrsw60t59b[1] (Page-table reserved-for-
> software bits 60-59) extension, and it will be a new part of RVA23.1[2].
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv/svrsw60t59b.adoc
> [2] https://github.com/riscv/riscv-isa-manual/pull/3170
>
> gcc/ChangeLog:
>
> 	* config/riscv/riscv-ext.def (svrsw60t59b): Add new extension.
> 	* config/riscv/riscv-ext.opt: Ditto.
> 	* doc/riscv-ext.texi: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/riscv/svrsw60t59b-version.c: New test.
OK.  Usual comments about DESC/URL apply.

jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 2100f2f6fc9..c3521761ff8 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -2172,6 +2172,19 @@  DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ svrsw60t59b,
+  /* UPPERCASE_NAME */ SVRSW60T59B,
+  /* FULL_NAME */ "Page-table reserved-for-software bits 60-59 extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ sv,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ svvptc,
   /* UPPERCASE_NAME */ SVVPTC,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 380d7f6b577..2b4bbf3b910 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -423,6 +423,8 @@  Mask(SVNAPOT) Var(riscv_sv_subext)
 
 Mask(SVPBMT) Var(riscv_sv_subext)
 
+Mask(SVRSW60T59B) Var(riscv_sv_subext)
+
 Mask(SVVPTC) Var(riscv_sv_subext)
 
 Mask(SVADU) Var(riscv_sv_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 1fba663b4ef..30d4ede3457 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -646,6 +646,10 @@ 
 @tab 1.0
 @tab Page-based memory types extension
 
+@item @samp{svrsw60t59b}
+@tab 1.0
+@tab Page-table reserved-for-software bits 60-59 extension
+
 @item @samp{svvptc}
 @tab 1.0
 @tab Extension for obviating memory-management instructions after marking PTEs valid
diff --git a/gcc/testsuite/gcc.target/riscv/svrsw60t59b-version.c b/gcc/testsuite/gcc.target/riscv/svrsw60t59b-version.c
new file mode 100644
index 00000000000..8d130fbd233
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/svrsw60t59b-version.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_svrsw60t59b1p0 -mabi=lp64" { target { rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_svrsw60t59b1p0 -mabi=ilp32" { target { rv32 } } } */
+
+#ifndef __riscv_svrsw60t59b
+#error "Feature macro for 'svrsw60t59b' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, .*svrsw60t59b1p0" } } */