diff mbox series

[v3,10/14] MIPS: Inefficient scattered double precision load in MSA

Message ID 20260717125453.74473-11-eldar.osmanovic@htecgroup.com
State New
Headers
Series Mips target improvements |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Build passed

Commit Message

Eldar Osmanovic July 17, 2026, 12:56 p.m. UTC 
  From: Mihailo Stojanovic <mihailo.stojanovic@rt-rk.com>

Prevent combine from creating vector duplicate patterns when the source
register is wider than a target word. This rejects unsupported 64-bit
scalar duplication patterns on 32-bit MIPS targets.

gcc/ChangeLog:

	* config/mips/mips.cc (mips_legitimate_combined_insn):
	New function.

gcc/testsuite/ChangeLog:

	* gcc.target/mips/msa-combine-fill-d.c: New test.

Cherry-picked 092a39db956a418e7e020107b062c170ed976841
from https://github.com/MIPS/gcc

Signed-off-by: Mihailo Stojanovic <mistojanovic@wavecomp.com>
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
Signed-off-by: Eldar Osmanovic <eldar.osmanovic@htecgroup.com>
---
 gcc/config/mips/mips.cc                       | 19 +++++++++++++++++++
 .../gcc.target/mips/msa-combine-fill-d.c      | 13 +++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/msa-combine-fill-d.c
diff mbox series

Patch

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 0a1792434ad..b6c90d97b33 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -24641,6 +24641,22 @@  mips_c_mode_for_floating_type (enum tree_index ti)
   return default_mode_for_floating_type (ti);
 }
 
+/* Implement TARGET_LEGITIMATE_COMBINED_INSN hook.  */
+
+static bool
+mips_legitimate_combined_insn (rtx_insn *insn)
+{
+  rtx p = PATTERN (insn);
+  if (GET_CODE (p) == SET
+      && GET_CODE (XEXP (p, 1)) == VEC_DUPLICATE
+      && GET_CODE (XEXP (XEXP (p, 1), 0)) == REG
+      && (GET_MODE_UNIT_SIZE (GET_MODE (XEXP (XEXP (p, 1), 0)))
+	  > UNITS_PER_WORD))
+    return false;
+
+  return true;
+}
+
 void
 mips_bit_clear_info (enum machine_mode mode, unsigned HOST_WIDE_INT m,
 		      int *start_pos, int *size)
@@ -24983,6 +24999,9 @@  mips_print_patchable_function_entry (FILE *file ATTRIBUTE_UNUSED,
 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
 
+#undef TARGET_LEGITIMATE_COMBINED_INSN
+#define TARGET_LEGITIMATE_COMBINED_INSN mips_legitimate_combined_insn
+
 #undef TARGET_HARD_REGNO_SCRATCH_OK
 #define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
 
diff --git a/gcc/testsuite/gcc.target/mips/msa-combine-fill-d.c b/gcc/testsuite/gcc.target/mips/msa-combine-fill-d.c
new file mode 100644
index 00000000000..2283ece6b31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-combine-fill-d.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mno-mips16 -mfp64 -mhard-float -mmsa -fdump-rtl-combine-details" } */
+/* { dg-skip-if "needs combine" { *-*-* } { "-O0" } { "" } } */
+
+typedef long long v2i64 __attribute__((vector_size (16)));
+
+v2i64
+foo (long long x)
+{
+  return (v2i64) { x, x };
+}
+
+/* { dg-final { scan-rtl-dump "Instruction not appropriate for target" "combine" { target { ! mips64 } } } } */