[v1,5/5] RISC-V: Adjust test case due to vf[sz]ext.vf4 overlap

Message ID 20260708142206.215039-6-pan2.li@intel.com
State Committed
Delegated to: Robin Dapp
Headers
Series Support RVV register overlap for v[sz]ext.vf4 |

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Commit Message

Li, Pan2 July 8, 2026, 2:20 p.m. UTC
  From: Pan Li <pan2.li@intel.com>

Remove the xfail due to vf4 changes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr112431-16.c: Remove xfail.
	* gcc.target/riscv/rvv/base/pr112431-17.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
  

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
index 42d11611d98..98f42458883 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
@@ -65,4 +65,4 @@  foo (char const *buf, size_t len)
 /* { dg-final { scan-assembler-not {vmv2r} } } */
 /* { dg-final { scan-assembler-not {vmv4r} } } */
 /* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
index 9ecc62e234b..9b60005344d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
@@ -48,4 +48,4 @@  foo (char const *buf, size_t len)
 /* { dg-final { scan-assembler-not {vmv2r} } } */
 /* { dg-final { scan-assembler-not {vmv4r} } } */
 /* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */