diff mbox series

[v1,3/5] RISC-V: Add test cases for vzext.vf4 reg overlap

Message ID 20260708142206.215039-4-pan2.li@intel.com
State Committed
Delegated to: Robin Dapp
Headers
Series Support RVV register overlap for v[sz]ext.vf4 |

Checks

Context Check Description
rivoscibot/toolchain-ci-rivos-lint success Lint passed
rivoscibot/toolchain-ci-rivos-apply-patch success Patch applied
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rivoscibot/toolchain-ci-rivos-build--linux-rv64gcv-lp64d-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--linux-rv64gc_zba_zbb_zbc_zbs-lp64d-multilib success Build passed
rivoscibot/toolchain-ci-rivos-test fail Testing failed

Commit Message

Li, Pan2 July 8, 2026, 2:20 p.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Add test cases for vzext.vf4 register group overlap, please
note it is not overlap as much as possible.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../autovec/group_overlap/vzext_vf4-u16-m1.c  | 17 ++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u16-m2.c  | 17 ++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u16-mf2.c | 23 +++++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u16-mf4.c | 23 +++++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-m1.c   | 17 ++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-m2.c   | 17 ++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-mf2.c  | 23 +++++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-mf4.c  | 23 +++++++++++++++++++
 .../autovec/group_overlap/vzext_vf4-u8-mf8.c  | 23 +++++++++++++++++++
 9 files changed, 183 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c
new file mode 100644
index 00000000000..cce2d1a9426
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m1,
+  vuint16m1_t,
+  vuint64m4_t,
+  __riscv_vle16_v_u16m1,
+  __riscv_vzext_vf4_u64m4,
+  __riscv_vse64_v_u64m4,
+  vzext_vf,
+  LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v4,v7} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c
new file mode 100644
index 00000000000..845917e4eea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m2,
+  vuint16m2_t,
+  vuint64m8_t,
+  __riscv_vle16_v_u16m2,
+  __riscv_vzext_vf4_u64m8,
+  __riscv_vse64_v_u64m8,
+  vzext_vf,
+  LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v6} 1 } } */
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v8,v14} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c
new file mode 100644
index 00000000000..c56b984c5c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m1,
+  vuint16mf2_t,
+  vuint64m2_t,
+  __riscv_vle16_v_u16mf2,
+  __riscv_vzext_vf4_u64m2,
+  __riscv_vse64_v_u64m2,
+  vzext_vf,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c
new file mode 100644
index 00000000000..055839b8e94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e16m1,
+  vuint16mf4_t,
+  vuint64m1_t,
+  __riscv_vle16_v_u16mf4,
+  __riscv_vzext_vf4_u64m1,
+  __riscv_vse64_v_u64m1,
+  vzext_vf,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c
new file mode 100644
index 00000000000..525be7621a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m1,
+  vuint8m1_t,
+  vuint32m4_t,
+  __riscv_vle8_v_u8m1,
+  __riscv_vzext_vf4_u32m4,
+  __riscv_vse32_v_u32m4,
+  vzext_vf,
+  LOOP_UNARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v4,v7} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c
new file mode 100644
index 00000000000..159808de53a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m2,
+  vuint8m2_t,
+  vuint32m8_t,
+  __riscv_vle8_v_u8m2,
+  __riscv_vzext_vf4_u32m8,
+  __riscv_vse32_v_u32m8,
+  vzext_vf,
+  LOOP_UNARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v6} 1 } } */
+/* { dg-final { scan-assembler-times {vzext\.vf4\s+v8,v14} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c
new file mode 100644
index 00000000000..9188968bb95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf2_t,
+  vuint32m2_t,
+  __riscv_vle8_v_u8mf2,
+  __riscv_vzext_vf4_u32m2,
+  __riscv_vse32_v_u32m2,
+  vzext_vf,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c
new file mode 100644
index 00000000000..b5d233b5d6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf4_t,
+  vuint32m1_t,
+  __riscv_vle8_v_u8mf4,
+  __riscv_vzext_vf4_u32m1,
+  __riscv_vse32_v_u32m1,
+  vzext_vf,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c
new file mode 100644
index 00000000000..a8aab4cfc0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c
@@ -0,0 +1,23 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_UNARY_0(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf8_t,
+  vuint32mf2_t,
+  __riscv_vle8_v_u8mf8,
+  __riscv_vzext_vf4_u32mf2,
+  __riscv_vse32_v_u32mf2,
+  vzext_vf,
+  LOOP_UNARY_BODY_X16)
+
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */
+/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */