diff mbox series

RISC-V: Enable TARGET_SFB_ALU for andes-45-series

Message ID 20260708024635.139877-1-jim@andestech.com
State Committed
Commit 05c929c143c5dea121e78092a1eaad9a422022a9
Headers
Series RISC-V: Enable TARGET_SFB_ALU for andes-45-series |

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Commit Message

Jim Lin July 8, 2026, 2:46 a.m. UTC 
  Enable short forward branch (SFB) ALU support for the andes-45-series
tune, matching the existing sfb_alu scheduling reservation already
present in andes-45-series.md.

gcc/ChangeLog:

	* config/riscv/riscv.h (TARGET_SFB_ALU): Add andes_45_series.
---
 gcc/config/riscv/riscv.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Kito Cheng July 8, 2026, 2:59 a.m. UTC | #1 
LGTM :)

Jim Lin <jim@andestech.com> 於 2026年7月8日週三 上午10:47寫道：

>
> Enable short forward branch (SFB) ALU support for the andes-45-series
> tune, matching the existing sfb_alu scheduling reservation already
> present in andes-45-series.md.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.h (TARGET_SFB_ALU): Add andes_45_series.
> ---
>  gcc/config/riscv/riscv.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index d72c06ec37f..7eb85d654a7 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -974,7 +974,8 @@ extern enum riscv_cc get_riscv_cc (const rtx use);
>  #define TARGET_SFB_ALU \
>   ((riscv_microarchitecture == sifive_7) \
>    || (riscv_microarchitecture == sifive_p400) \
> -  || (riscv_microarchitecture == sifive_p600))
> +  || (riscv_microarchitecture == sifive_p600) \
> +  || (riscv_microarchitecture == andes_45_series))
>
>  /* True if the target supports misaligned vector loads and stores.  */
>  #define TARGET_VECTOR_MISALIGN_SUPPORTED \
> --
> 2.52.0
>
Jeffrey Law July 8, 2026, 11:57 p.m. UTC | #2 
On 7/7/2026 8:59 PM, Kito Cheng wrote:
> LGTM :)
Agreed and pushed.

However, I'm going to have to pause integration of further patches from 
Jim until he either starts including a DCO signoff in the patch itself, 
adds himself to the DCO section of the MAINTAINERS file or gets an 
past/future assignment in place with the FSF.   While none of the 
patches individually are significant from a copyright standpoint, the 
aggregate of the patches probably does push us into the significant from 
a copyright standpoint.

Jeff
Kito Cheng July 9, 2026, 2:56 a.m. UTC | #3 
> However, I'm going to have to pause integration of further patches from
> Jim until he either starts including a DCO signoff in the patch itself,
> adds himself to the DCO section of the MAINTAINERS file or gets an
> past/future assignment in place with the FSF.   While none of the
> patches individually are significant from a copyright standpoint, the
> aggregate of the patches probably does push us into the significant from
> a copyright standpoint.

IIRC andestech has signed company-wise copyright assignment for GNU toolchains?
He still needs DCO signoff even if they have that?

>
> Jeff
>
Kito Cheng July 9, 2026, 3:10 a.m. UTC | #4 
Follow up: I checked fencepost.gnu.org again and I saw they have
signed for GLIBC GDB GCC BINUTILS since 2009 :)

Kito Cheng <kito.cheng@gmail.com> 於 2026年7月9日週四 上午10:56寫道：
>
> > However, I'm going to have to pause integration of further patches from
> > Jim until he either starts including a DCO signoff in the patch itself,
> > adds himself to the DCO section of the MAINTAINERS file or gets an
> > past/future assignment in place with the FSF.   While none of the
> > patches individually are significant from a copyright standpoint, the
> > aggregate of the patches probably does push us into the significant from
> > a copyright standpoint.
>
> IIRC andestech has signed company-wise copyright assignment for GNU toolchains?
> He still needs DCO signoff even if they have that?
>
> >
> > Jeff
> >
Jeffrey Law July 9, 2026, 1:21 p.m. UTC | #5 
On 7/8/2026 9:10 PM, Kito Cheng wrote:
> Follow up: I checked fencepost.gnu.org again and I saw they have
> signed for GLIBC GDB GCC BINUTILS since 2009 :)
Oh, good.  Thanks.  Pause lifted :-)

jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index d72c06ec37f..7eb85d654a7 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -974,7 +974,8 @@  extern enum riscv_cc get_riscv_cc (const rtx use);
 #define TARGET_SFB_ALU \
  ((riscv_microarchitecture == sifive_7) \
   || (riscv_microarchitecture == sifive_p400) \
-  || (riscv_microarchitecture == sifive_p600))
+  || (riscv_microarchitecture == sifive_p600) \
+  || (riscv_microarchitecture == andes_45_series))
 
 /* True if the target supports misaligned vector loads and stores.  */
 #define TARGET_VECTOR_MISALIGN_SUPPORTED \