diff mbox series

[v1,1/2] RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost

Message ID 20260506015845.2306182-2-pan2.li@intel.com
State Committed
Delegated to: Robin Dapp
Headers
Series RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost |

Checks

Context Check Description
rivoscibot/toolchain-ci-rivos-lint success Lint passed
rivoscibot/toolchain-ci-rivos-apply-patch success Patch applied
rivoscibot/toolchain-ci-rivos-build--linux-rv64gc_zba_zbb_zbc_zbs-lp64d-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--newlib-rv64gcv-lp64d-multilib success Build passed
rivoscibot/toolchain-ci-rivos-build--linux-rv64gcv-lp64d-multilib success Build passed
rivoscibot/toolchain-ci-rivos-test pending Testing started

Commit Message

Li, Pan2 May 6, 2026, 1:57 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

This patch would like to combine the vec_duplicate + vmsgt.vv to the
vmsgt.vx.  From example as below code.  The related pattern will depend
on the cost of vec_duplicate from GR2VR.  Then the late-combine will
take action if the cost of GR2VR is zero, and reject the combination
if the GR2VR cost is greater than zero.

Assume we have asm code like below, GR2VR cost is 0.

Before this patch:
  11       beq a3,zero,.L8
  12       vsetvli a5,zero,e32,m1,ta,ma
  13       vmv.v.x v2,a2
  ...
  16   .L3:
  17       vsetvli a5,a3,e32,m1,ta,ma
  ...
  22       vmsgt.vv v1,v2,v3
  ...
  25       bne a3,zero,.L3

After this patch:
  11       beq a3,zero,.L8
  ...
  14    .L3:
  15       vsetvli a5,a3,e32,m1,ta,ma
  ...
  20       vmsgt.vx v1,a2,v3
  ...
  23       bne a3,zero,.L3

gcc/ChangeLog:

	* config/riscv/predicates.md: Add lt to swapped operator.
	* config/riscv/riscv-v.cc (get_swapped_cmp_rtx_code): Handle
	the rtl as well.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/predicates.md | 2 +-
 gcc/config/riscv/riscv-v.cc    | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 4116674601c..47e634ad87f 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -612,7 +612,7 @@  (define_predicate "comparison_except_ge_operator"
   (match_code "eq,ne,le,leu,gt,gtu,lt,ltu"))
 
 (define_predicate "comparison_swappable_operator"
-  (match_code "gtu,gt,geu,ge,ltu"))
+  (match_code "gtu,gt,geu,ge,ltu,lt"))
 
 (define_predicate "ge_operator"
   (match_code "ge,geu"))
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 3c7e749cb60..7318fda7758 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -6075,6 +6075,8 @@  get_swapped_cmp_rtx_code (rtx_code code)
       return LE;
     case LTU:
       return GTU;
+    case LT:
+      return GT;
     default:
       gcc_unreachable ();
     }