diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a6106547757..b743d3533f2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -15919,7 +15919,7 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
 {
   /* Trivial cases that don't need synthesis.  */
   if (SMALL_OPERAND (INTVAL (operands[2]))
-     || ((TARGET_ZBS || TARGET_ZBKB)
+     || (TARGET_ZBS
 	 && single_bit_mask_operand (operands[2], word_mode)))
     return false;
 
diff --git a/gcc/testsuite/gcc.target/riscv/pr124818.c b/gcc/testsuite/gcc.target/riscv/pr124818.c
new file mode 100644
index 00000000000..a629e8e96a2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr124818.c
@@ -0,0 +1,9 @@
+/* { dg-do compile { target { riscv32*-*-* } } } */
+/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */
+
+int
+f (unsigned int *flags)
+{
+  *flags |= 0x20000U;
+  return 1;
+}