From patchwork Sun Dec 7 00:10:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandra Loosemore X-Patchwork-Id: 126084 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8AC2E4B94CC4 for ; Sun, 7 Dec 2025 00:25:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8AC2E4B94CC4 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=QZD6kTj1 X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-f68.google.com (mail-ot1-f68.google.com [209.85.210.68]) by sourceware.org (Postfix) with ESMTPS id 5D4E041436E2 for ; Sun, 7 Dec 2025 00:11:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5D4E041436E2 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=baylibre.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5D4E041436E2 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=209.85.210.68 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1765066269; cv=none; b=XPUhvOrspuqdtr22TosvO7NGJAa6EoevuD4XBVYp89OKHhC2YWkSRM2T7D5hXFyTYwWcweKVc2+swehz4e6T4oDge3JCcHyKmRgyb7QsubwGnoS0te+AS00LPzndtjqYU6iybuhqauK7LHufv3PIxh7cDYaEw+z8OaU9H9Fx5fo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1765066269; c=relaxed/simple; bh=7JlhsfHambQevURejkt8JQ8/CfLIpmyHz0S4lUu7NW0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=JaYbK+geUTXr5Nafs5yEaqsZWkhexT6d5JlfemtA7ALEeWSpxrabSQKn8v+yWC+lCTDcjLhhoO6kMryQaskihqbvpCT9prBtvARdrrHeO0QGW2S9QS06mKXrJWz/cA8gi2DuRo+/F2u9VzeFbozPu1qoNn7mj7nqz3pa3t6OzS8= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5D4E041436E2 Received: by mail-ot1-f68.google.com with SMTP id 46e09a7af769-7c6ce4f65f7so3202113a34.0 for ; Sat, 06 Dec 2025 16:11:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1765066269; x=1765671069; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t/C3gbu/K8+bc6PQJaNJqfeqUxRLSeJL6KVlEUHBpzg=; b=QZD6kTj1dwKlLv/KCdpVCADWWUqGNXbqpacK3pZkCUr8FHmg3fhyIGJo0WS1iBullg oEm3cgZFmDRUZIWOpR0gLHO65u1zL0h9GERKAQeLXa3l4QwJE5hZVHW547dcP2quB9a8 Ts1GVxcoC+NljfBYcgD8A8dTjlfxiiCCkQHWC2gRl/rLZ02haAGkAq5jRjaZ3zEVyi56 ldqzVLZu+tBz0IPtEGNVQLWzNF+iSHoQxFo9erqVeqoCd+AwZY/w+Q+2GFYMiog5nwfv 87MvyygoRU3j8dxpSqUi/GDIEiPtq4G7Q/JuglMRabwd4xU6LVcZOxyjLMCqox33sCK0 zwnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765066269; x=1765671069; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=t/C3gbu/K8+bc6PQJaNJqfeqUxRLSeJL6KVlEUHBpzg=; b=a1zaz6M8ryMcE0DHFA0CQQa+P0DbSnQOuDXx/4TLD/iOEz8qTNHMKos9o2P9RBjilw DXRPcjjI24ySVe6FdoLVDM6XjQdeU2AOKi8tFhocLjN0ELtZIDP3XDveq5kZN9U1IwGK sB1++hrN0JnxIi1y7f9ffTA0yB10ljJIMqH2gY7RcYDMVsJBdQ5MBagbdq8z4nV79l3C SOAAuZfWm4LYyD318Gwdz/cgTDQC/wK0A0jMDfkhjeM/xnQKh3VJB6MdoOpJk7OTXER4 8pRjaEwP22d7nzT8ZvEHMtaVQeeD4GlPlsu+qvziBZFZmV48kquDCtgvIujqMH3mWFn3 mUwQ== X-Gm-Message-State: AOJu0YyOBQ02/XScoyK5YbUUtT0Dv0MSa3CvYc1wHU2tZNsCnx6ioysQ jEXFJx5rP1PYxnLQGotT+WfFAuR9L2mdss6ezB0rgURPjb2C/2w2rdtT9II7z577BuPXbDT4evH xiBMx8y0= X-Gm-Gg: ASbGncvRwkwTGPYcRc5V/g6K5uUuTwhHEbWYaluAQQAyaC+PPwIiSnNagLnXsk+XH54 n49jSDTOdVCuApBBxd8JRcVX172gjrpL9XsmWT9J6TtCYRmj1B66REmsqUiIARw8kSG3Zh5qhMu ZrgIWzFyybPW3tE/xP0PfDhJ1rPozEQSeBOyrlhUh20pcRpTutv9XiYN3V7FRAW23BlfYMDu1NK xmbzxxu7p/+ZUbIzE3GsorOyvHx3GUMW6JHZemLy/7h5MY99iK239CaejSGFfr7OU9NpMsgaaRP OfRdWhSYE7mZPxX53J9m6fFZzLet5aSvZjoL2fBwz9BhybwVX7KHsCCyT2fv2ezYi+FREaNT+c1 l/BILp13GemoHWcgph9DFJTGv7esXUSlIY7GQpLcoYtxLNygK8/NQAKD6U/vgT/vjjzqdr/kzKp PPg/8T25vSXa2Z X-Google-Smtp-Source: AGHT+IHWx4G88CplMCmVnnVIelj5BlCU4+EYdBURWd095e+6afx+6AIzLX+qI6hV8Aqb8NCXzt86WQ== X-Received: by 2002:a05:6830:411f:b0:7c3:e07f:568f with SMTP id 46e09a7af769-7c97076f7f8mr3009873a34.8.1765066268713; Sat, 06 Dec 2025 16:11:08 -0800 (PST) Received: from localhost.localdomain ([2601:281:d901:97c0::6b05]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c95a8f8d0bsm7598391a34.5.2025.12.06.16.11.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Dec 2025 16:11:08 -0800 (PST) From: Sandra Loosemore To: gcc-patches@gcc.gnu.org Cc: tdevries@suse.de, tschwinge@baylibre.com Subject: [PATCH 17/20] doc, nvptx: Clean up documentation of Nvidia PDX Options [PR122243] Date: Sat, 6 Dec 2025 17:10:27 -0700 Message-Id: <20251207001030.1024365-18-sloosemore@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251207001030.1024365-1-sloosemore@baylibre.com> References: <20251207001030.1024365-1-sloosemore@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog PR other/122243 * doc/invoke.texi (Option Summary) : Add several missing options. (Nvidia PTX Options): Correct index entry for -march-map. List negative forms of -moptimize, muniform-simt, and -mgomp. Fix some Texinfo markup issues. --- gcc/doc/invoke.texi | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 77ba685d560..62afc5a66dd 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1280,7 +1280,9 @@ Objective-C and Objective-C++ Dialects}. -mctor-dtor -mrelax} @emph{Nvidia PTX Options} (@ref{Nvidia PTX Options}) -@gccoptlist{-m64 -mmainkernel -moptimize} +@gccoptlist{-m64 -march=@var{arch} -misa=@var{arch} -march-map=@var{arch} +-mptx=@var{version} +-mmainkernel -moptimize -msoft-stack -muniform-simt -mgomp} @emph{OpenRISC Options} (@ref{OpenRISC Options}) @gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @@ -31480,7 +31482,7 @@ This option sets the value of the preprocessor macro @item -misa=@var{architecture-string} Alias of @option{-march=}. -@opindex march +@opindex march-map @item -march-map=@var{architecture-string} Select the closest available @option{-march=} value that is not more capable. For instance, for @option{-march-map=sm_50} select @@ -31511,9 +31513,11 @@ Link in code for a __main kernel. This is for stand-alone instead of offloading execution. @opindex moptimize +@opindex mno-optimize @item -moptimize -Apply partitioned execution optimizations. This is the default when any -level of optimization is selected. +@itemx -mno-optimize +Enable/disable partitioned execution optimizations. This option is enabled by +default when any level of optimization is selected. @opindex msoft-stack @opindex mno-soft-stack @@ -31539,11 +31543,15 @@ of testing the compiler; to generate code suitable for linking into programs using OpenMP offloading, use option @option{-mgomp}. @opindex muniform-simt +@opindex mno-uniform-simt @item -muniform-simt -Switch to code generation variant that allows to execute all threads in each +@itemx -mno-uniform-simt +Enable/disable code generation variant that allows execution of +all threads in each warp, while maintaining memory state and side effects as if only one thread in each warp was active outside of OpenMP SIMD regions. All atomic operations -and calls to runtime (malloc, free, vprintf) are conditionally executed (iff +and calls to runtime (@code{malloc}, @code{free}, @code{vprintf}) +are conditionally executed (iff current lane index equals the master lane index), and the register being assigned is copied via a shuffle instruction from the master lane. Outside of SIMD regions lane 0 is the master; inside, each thread sees itself as the @@ -31553,9 +31561,12 @@ regions). Each thread can bitwise-and the bitmask at position @code{tid.y} with current lane index to compute the master lane index. @opindex mgomp +@opindex mno-gomp @item -mgomp -Generate code for use in OpenMP offloading: enables @option{-msoft-stack} and -@option{-muniform-simt} options, and selects corresponding multilib variant. +@itemx -mno-gomp +Enable/disable generation of code for use in OpenMP offloading. +@option{-mgomp} enables @option{-msoft-stack} and +@option{-muniform-simt} options, and selects a corresponding multilib variant. @end table