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d="scan'208";a="179303086" Received: from panli.sh.intel.com ([10.239.159.63]) by fmviesa005.fm.intel.com with ESMTP; 16 Sep 2025 04:53:53 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v2 2/4] RISC-V: Add test for vec_duplicate + vwaddu.vv signed combine with GR2VR cost 0, 1 and 15 Date: Tue, 16 Sep 2025 19:52:39 +0800 Message-ID: <20250916115428.1176402-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916115428.1176402-1-pan2.li@intel.com> References: <20250916115428.1176402-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Add asm dump check and run test for vec_duplicate + vwaddu.vv combine to vwaddu.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vwaddu.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 4 + .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 4 + .../rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c | 18 +++++ .../riscv/rvv/autovec/vx_vf/vx_widen.h | 34 ++++++++ .../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 79 +++++++++++++++++++ .../riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h | 27 +++++++ 13 files changed, 194 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index d191097e2bb..bb29ef5638c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint16_t +#define NT uint8_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index e0b4b732c79..1d738571b49 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint32_t +#define NT uint16_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index 65528400b5b..dc6d1c6b183 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint64_t +#define NT uint32_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ @@ -29,3 +32,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index 23479d97b65..c6da9c7e19d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint16_t +#define NT uint8_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 8c41bd85686..6f1adef686c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint32_t +#define NT uint16_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index abe16cd7b50..5ea7cc96ae6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint64_t +#define NT uint32_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index f232d6a97bd..f18409e7643 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint16_t +#define NT uint8_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 24e187ce2b0..b33d8269136 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint32_t +#define NT uint32_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index 977aa463232..40f4142a88a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -3,11 +3,14 @@ #include "vx_binary.h" #include "vx_ternary.h" +#include "vx_widen.h" #define T uint64_t +#define NT uint32_t TEST_BINARY_VX_UNSIGNED_0(T) TEST_TERNARY_VX_UNSIGNED_0(T) +TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -26,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vnmsac.vx} } } */ /* { dg-final { scan-assembler-not {vmadd.vx} } } */ /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ +/* { dg-final { scan-assembler-not {vwaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c new file mode 100644 index 00000000000..e7a75d56f77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwaddu-run-1-u64.c @@ -0,0 +1,18 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_widen.h" +#include "vx_widen_data.h" + +#define WT uint64_t +#define NT uint32_t +#define NAME add +#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) +#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) + +DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, NAME) + +#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \ + RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N) + +#include "vx_widen_vx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h new file mode 100644 index 00000000000..646edab4310 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h @@ -0,0 +1,34 @@ +#ifndef HAVE_DEFINED_VX_VF_BINARY_WIDEN_H +#define HAVE_DEFINED_VX_VF_BINARY_WIDEN_H + +#include + +#undef HAS_INT128 + +#if __riscv_xlen == 64 +#define HAS_INT128 +typedef unsigned __int128 uint128_t; +typedef signed __int128 int128_t; +#endif + +#define DEF_VX_WIDEN_BINARY_CASE_0(WT, NT, OP, NAME) \ +void \ +test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \ + NT * restrict vs2, \ + NT rs1, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + vd[i] = (WT)vs2[i] OP (WT)rs1; \ +} + +#define DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, OP, NAME) \ + DEF_VX_WIDEN_BINARY_CASE_0(WT, NT, OP, NAME) +#define RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) \ + test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0(vd, vs2, rs1, n) +#define RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \ + RUN_VX_WIDEN_BINARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) + +#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \ + DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h new file mode 100644 index 00000000000..48dc4d4c849 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h @@ -0,0 +1,79 @@ +#ifndef HAVE_DEFINED_VX_WIDEN_DATA_H +#define HAVE_DEFINED_VX_WIDEN_DATA_H + +#define N 16 + +#define DEF_BINARY_WIDEN_STRUCT_0_NAME(WT, NT, NAME) \ + binary_widen_##WT##_##NT##_##NAME##_s +#define DEF_BINARY_WIDEN_STRUCT_0_NAME_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_NAME(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_0_TYPE(WT, NT, NAME) \ + struct DEF_BINARY_WIDEN_STRUCT_0_NAME_WRAP(WT, NT, NAME) +#define DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_TYPE(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_0_VAR(WT, NT, NAME) \ + binary_widen_##WT##_##NT##_##NAME##_data +#define DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_VAR(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_0_DECL(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) +#define DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_DECL(WT, NT, NAME) + +#define DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) \ + { \ + NT vs2[N]; \ + NT rs1; \ + WT expect[N]; \ + WT vd[N]; \ + }; +#define DEF_BINARY_WIDEN_STRUCT_0_WRAP(WT, NT, NAME) \ + DEF_BINARY_WIDEN_STRUCT_0(WT, NT, NAME) + +DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add) + +DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = { + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + /* rs1 */ + 2147483647, + /* expect */ + { + 2147483648, 2147483648, 2147483648, 2147483648, + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + }, + /* rs1 */ + 4294967295, + /* expect */ + { + 4294967296ull, 4294967296ull, 4294967296ull, 4294967296ull, + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 8589934590ull, 8589934590ull, 8589934590ull, 8589934590ull, + 8589934589ull, 8589934589ull, 8589934589ull, 8589934589ull, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h new file mode 100644 index 00000000000..87fe0b13215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_vx_run.h @@ -0,0 +1,27 @@ +#ifndef HAVE_DEFINED_VX_WIDEN_RUN_H +#define HAVE_DEFINED_VX_WIDEN_RUN_H + +int +main () +{ + unsigned i, k; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + DATA_TYPE *data = &TEST_DATA[i]; + NT *vs2 = data->vs2; + NT rs1 = data->rs1; + WT *expect = data->expect; + WT *vd = data->vd; + + TEST_RUN (WT, NT, NAME, vd, vs2, rs1, N); + + for (k = 0; k < N; k++) + if (vd[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif