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Mon, 15 Sep 2025 15:23:00 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 495kb0q8sp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Sep 2025 15:22:59 +0000 Received: from smtpav01.fra02v.mail.ibm.com (smtpav01.fra02v.mail.ibm.com [10.20.54.100]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 58FFMuBX31785410 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 15 Sep 2025 15:22:56 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 19ADF20040; Mon, 15 Sep 2025 15:22:56 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 06BCD20043; Mon, 15 Sep 2025 15:22:55 +0000 (GMT) Received: from nilram.aus.stglabs.ibm.com (unknown [9.5.12.132]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 15 Sep 2025 15:22:54 +0000 (GMT) From: Kishan Parmar To: gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, jskumari@linux.ibm.com Cc: meissner@linux.ibm.com, Kishan Parmar Subject: [PATCH] simplify-rtx: Canonicalize subreg and lshiftrt order for AND operations Date: Mon, 15 Sep 2025 10:22:44 -0500 Message-ID: <20250915152244.1192004-1-kishan@linux.ibm.com> X-Mailer: git-send-email 2.47.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTEzMDAyMCBTYWx0ZWRfX1FYLuQCHhSuX 4FmQY5W+APMyewlPaF88FbI9eBwJw0PhTA6qxk0d2gtgY4O8f9TCihyVT/jtSU4jCYX7o87+zot wi+iCcjbcnpVUy01Z2dMaV70z3sfuqbD/n2AxoK+tQuTlfRHxyjn3DD6iolHf8nHDxDBM86eGBd 10unSbUfelPM4s5cUhZ+WwrWn6M+6u7+JhahLFgrRmolC57K/3Fu8+WctbM8zWUIXjirETxocyp z2Ls8tFB1JamIvLJmv8ztz8juX5BrVMYz5bNd/Li1ExnQxstK5HIundNfCluZkKfWlikoQq5X0r O4H8HGDVsIcWVRFCavQHgxoct8mszx6a7uqt8yg+Gf9cDR5Xi/p3QzugHLDc8gWACn3Q2v4MSEo bt9qkJ9U X-Authority-Analysis: v=2.4 cv=OPYn3TaB c=1 sm=1 tr=0 ts=68c82f55 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=yJojWOMRYYMA:10 a=VnNF1IyMAAAA:8 a=HAcmdRAlfNCsdm8Hx0sA:9 X-Proofpoint-GUID: 27uzkvm4ZLoH37BxlJc3xAVUGW8hsuOC X-Proofpoint-ORIG-GUID: 27uzkvm4ZLoH37BxlJc3xAVUGW8hsuOC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-15_06,2025-09-12_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 phishscore=0 suspectscore=0 spamscore=0 bulkscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509130020 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Hi All, For a given rtx expression (and (lshiftrt (subreg X) shift) mask) combine pass tries to simplify the RTL form to (and (subreg (lshiftrt X shift)) mask) where the SUBREG wraps the result of the shift. This leaves the AND and the shift in different modes, which complicates recognition. (and (lshiftrt (subreg X) shift) mask) where the SUBREG is inside the shift and both operations share the same mode. This form is easier to recognize across targets and enables cleaner pattern matching. This patch checks in simplify-rtx to perform this transformation when safe: the SUBREG must be a lowpart, the shift amount must be valid, and the precision of the operation must be preserved. Tested on powerpc64le-linux-gnu, powerpc64-linux-gnu, and x86_64-pc-linux-gnu with no regressions. On rs6000, the change reduces insn counts due to improved matching. 2025-09-15 Kishan Parmar gcc/ChangeLog: * simplify-rtx.cc (simplify_context::simplify_binary_operation_1): Canonicalize SUBREG(LSHIFTRT) into LSHIFTRT(SUBREG) when valid. gcc/testsuite/ChangeLog: * gcc.target/powerpc/rlwimi-2.c: Update expected rldicl count. --- gcc/simplify-rtx.cc | 40 +++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/rlwimi-2.c | 2 +- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index 8f0f16c865d..e9469f9db68 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -4112,7 +4112,47 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, not do an AND. */ if ((nzop0 & ~val1) == 0) return op0; + + + /* Canonicalize (and (subreg (lshiftrt X shift)) mask) into + (and (lshiftrt (subreg X) shift) mask). + + Keeps shift and AND in the same mode, improving recognition. + Only applied when subreg is a lowpart, shift is valid, + and no precision is lost. */ + if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0) + && GET_CODE (XEXP (op0 ,0)) == LSHIFTRT + && CONST_INT_P (XEXP (XEXP (op0 ,0), 1)) + && INTVAL (XEXP (XEXP (op0 ,0), 1)) >= 0 + && INTVAL (XEXP (XEXP (op0 ,0), 1)) < HOST_BITS_PER_WIDE_INT + && ((INTVAL (XEXP (XEXP (op0, 0), 1)) + + floor_log2 (val1)) + < GET_MODE_PRECISION (as_a (mode)))) + { + tem = XEXP (XEXP (op0, 0), 0); + if (GET_CODE (tem) == SUBREG) + { + if (subreg_lowpart_p (tem)) + tem = SUBREG_REG (tem); + else + goto no_xform; + } + offset = subreg_lowpart_offset (mode, GET_MODE (tem)); + tem = simplify_gen_subreg (mode, tem, GET_MODE (tem), + offset); + if (tem) + { + unsigned shiftamt = INTVAL (XEXP (XEXP (op0, 0), 1)); + rtx shiftamtrtx = gen_int_shift_amount (mode, + shiftamt); + op0 = simplify_gen_binary (LSHIFTRT, mode, tem, + shiftamtrtx); + return simplify_gen_binary (AND, mode, op0, op1); + + } + } } +no_xform: nzop1 = nonzero_bits (trueop1, mode); /* If we are clearing all the nonzero bits, the result is zero. */ if ((nzop1 & nzop0) == 0 diff --git a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c index bafa371db73..afbde0e5fc6 100644 --- a/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c +++ b/gcc/testsuite/gcc.target/powerpc/rlwimi-2.c @@ -6,7 +6,7 @@ /* { dg-final { scan-assembler-times {(?n)^\s+blr} 6750 } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mr} 643 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+mr} 11 { target lp64 } } } */ -/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 7790 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {(?n)^\s+rldicl} 6754 { target lp64 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1692 { target ilp32 } } } */ /* { dg-final { scan-assembler-times {(?n)^\s+rlwimi} 1666 { target lp64 } } } */