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d="scan'208";a="173285408" Received: from panli.sh.intel.com ([10.239.159.63]) by orviesa006.jf.intel.com with ESMTP; 12 Sep 2025 16:34:41 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 4/4] RISC-V: Add test for vec_duplicate + vwmulu.vv signed combine with GR2VR cost 0, 1 and 15 Date: Fri, 12 Sep 2025 22:14:33 +0800 Message-ID: <20250912233514.3586587-5-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250912233514.3586587-1-pan2.li@intel.com> References: <20250912233514.3586587-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Add asm dump check and run test for vec_duplicate + vwmulu.vv combine to vwmulu.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check for vwmulu.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test data for vwmulu.vx run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 + .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 + .../rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c | 18 +++++++++ .../riscv/rvv/autovec/vx_vf/vx_widen.h | 3 +- .../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 40 +++++++++++++++++++ 12 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index 25bb93c8ce5..c86461beadf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index 475b74b10f0..90de1974ab1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index c7f3f2b25d4..522ddd19ccd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -34,3 +34,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vwsubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index 1c0024c273e..6ea17bb83d9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 3e88fc0623f..8b8fba54b72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index 541b6e678b9..6f66de906a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index 6d25e26d83b..cd129f1f50e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index f0c6624a536..48aeed71eb9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index 8de1d6fd807..b88c350acf3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -31,3 +31,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vnmsub.vx} } } */ /* { dg-final { scan-assembler-not {vwaddu.vx} } } */ /* { dg-final { scan-assembler-not {vwsubu.vx} } } */ +/* { dg-final { scan-assembler-not {vwmulu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c new file mode 100644 index 00000000000..11c11eded43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmulu-run-1-u64.c @@ -0,0 +1,18 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_widen.h" +#include "vx_widen_data.h" + +#define WT uint64_t +#define NT uint32_t +#define NAME mul +#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME) +#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME) + +DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, NAME) + +#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \ + RUN_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N) + +#include "vx_widen_vx_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h index 290d8a4b5d4..998c05961ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h @@ -30,6 +30,7 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \ #define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \ DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \ - DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) + DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \ + DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, *, mul) \ #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h index 7359f0bc85d..5b49083abe7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h @@ -37,6 +37,7 @@ DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add) DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub) +DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul) DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, add)[] = { { @@ -116,4 +117,43 @@ DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, sub)[] = { }, }; +DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, mul)[] = { + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 9, 9, 9, 9, + }, + /* rs1 */ + 2147483647, + /* expect */ + { + 2147483647, 2147483647, 2147483647, 2147483647, + 0, 0, 0, 0, + 4294967294, 4294967294, 4294967294, 4294967294, + 19327352823ull, 19327352823ull, 19327352823ull, 19327352823ull, + }, + }, + { + /* vs2 */ + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 4294967294ull, 4294967294ull, 4294967294ull, 4294967294ull, + }, + /* rs1 */ + 4294967295, + /* expect */ + { + 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull, + 0, 0, 0, 0, + 18446744065119617025ull, 18446744065119617025ull, 18446744065119617025ull, 18446744065119617025ull, + 18446744060824649730ull, 18446744060824649730ull, 18446744060824649730ull, 18446744060824649730ull, + }, + }, +}; + #endif