diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 02f19bc6a42..fefd2dc63c3 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -1868,6 +1868,50 @@ (define_insn_and_split "*mul_minus_vx_<mode>"
   }
   [(set_attr "type" "vimuladd")])
 
+(define_insn_and_split "*widen_frist_<any_extend:su>_vx_<mode>"
+ [(set (match_operand:VWEXTI_D   0 "register_operand")
+       (vec_duplicate:VWEXTI_D
+	 (any_extend:<VEL>
+	 (match_operand:<VSUBEL> 1 "register_operand"))))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    machine_mode d_trunc_mode = <V_DOUBLE_TRUNC>mode;
+    rtx vec_dup = gen_reg_rtx (d_trunc_mode);
+    insn_code icode = code_for_pred_broadcast (d_trunc_mode);
+    rtx vec_dup_ops[] = {vec_dup, operands[1]};
+    riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, vec_dup_ops);
+
+    icode = code_for_pred_vf2 (<any_extend:CODE>, <MODE>mode);
+    rtx extend_ops[] = {operands[0], vec_dup};
+    riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, extend_ops);
+
+    DONE;
+  })
+
+(define_insn_and_split "*widen_<any_widen_binop:optab>_<any_extend:su>_vx_<mode>"
+ [(set (match_operand:VWEXTI_D             0 "register_operand")
+       (any_widen_binop:VWEXTI_D
+	 (any_extend:VWEXTI_D
+	   (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
+	 (vec_duplicate:VWEXTI_D
+	   (any_extend:<VEL>
+	     (match_operand:<VSUBEL>       2 "register_operand")))))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    insn_code icode = code_for_pred_dual_widen_scalar (<any_widen_binop:CODE>,
+						       <any_extend:extend_code>,
+						       <MODE>mode);
+    riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
+
+    DONE;
+  }
+  [(set_attr "type" "viwalu")])
 
 ;; =============================================================================
 ;; Combine vec_duplicate + op.vv to op.vf
diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index d3002241509..41e56c721c5 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -207,6 +207,9 @@ (define_mode_attr slot12_offset [(SI "-52") (DI "-104")])
 ;; This code iterator allows signed and unsigned widening multiplications
 ;; to use the same template.
 (define_code_iterator any_extend [sign_extend zero_extend])
+(define_code_attr extend_code [
+  (sign_extend "SIGN_EXTEND") (zero_extend "ZERO_EXTEND")
+])
 
 ;; These code iterators allow unsigned and signed extraction to be generated
 ;; from the same template.
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index ed7e9c3a951..45af65642cd 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -943,6 +943,22 @@ (define_mode_iterator V_FRACT [
   (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_VECTOR_ELEN_64")
 ])
 
+(define_mode_iterator VWEXTI_D [
+  (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
+  (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
+
+  (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64")
+  (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64")
+  (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64")
+  (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
+  (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+  (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
+  (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
+  (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
+  (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
+  (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
+])
+
 (define_mode_iterator VWEXTI [
   RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_VECTOR_ELEN_64")