diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7edc288a656..7621f5c4f0a 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -2107,6 +2107,14 @@
   "vsrv %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
+(define_insn "*altivec_vsl<VI_char>_const_1"
+  [(set (match_operand:VI2 0 "register_operand" "=v")
+	(ashift:VI2 (match_operand:VI2 1 "register_operand" "v")
+		      (match_operand:VI2 2 "vector_constant_1" "")))]
+  "<VI_unit>"
+  "vaddu<VI_char>m %0,%1,%1"
+)
+
 (define_insn "*altivec_vsl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (ashift:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 647e89afb6a..7a9c7df84ad 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -924,6 +924,17 @@
     }
 })
 
+(define_predicate "vector_constant_1"
+  (match_code "const_vector")
+{
+  unsigned nunits = GET_MODE_NUNITS (mode), i;
+  for (i = 0; i < nunits; i++) 
+    if (INTVAL (CONST_VECTOR_ELT(op, i)) != 1)
+      return 0;
+  
+  return 1;
+})
+
 ;; Return 1 if operand is 0.0.
 (define_predicate "zero_fp_constant"
   (and (match_code "const_double")
diff --git a/gcc/testsuite/gcc.target/powerpc/pr119702-1.c b/gcc/testsuite/gcc.target/powerpc/pr119702-1.c
new file mode 100644
index 00000000000..3f292cde9a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr119702-1.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+#include <inttypes.h>
+
+void lshift1_64(uint64_t *a) {
+  a[0] <<= 1;
+  a[1] <<= 1;
+}
+
+void lshift1_32(unsigned int *a) {
+  a[0] <<= 1;
+  a[1] <<= 1;
+  a[2] <<= 1;
+  a[3] <<= 1;
+}
+
+void lshift1_16(uint16_t *a) {
+  a[0] <<= 1;
+  a[1] <<= 1;
+  a[2] <<= 1;
+  a[3] <<= 1;
+  a[4] <<= 1;
+  a[5] <<= 1;
+  a[6] <<= 1;
+  a[7] <<= 1;
+}
+
+void lshift1_8(uint8_t *a) {
+  a[0] <<= 1;
+  a[1] <<= 1;
+  a[2] <<= 1;
+  a[3] <<= 1;
+  a[4] <<= 1;
+  a[5] <<= 1;
+  a[6] <<= 1;
+  a[7] <<= 1;
+  a[8] <<= 1;
+  a[9] <<= 1;
+  a[10] <<= 1;
+  a[11] <<= 1;
+  a[12] <<= 1;
+  a[13] <<= 1;
+  a[14] <<= 1;
+  a[15] <<= 1;
+}
+
+
+/* { dg-final { scan-assembler-times {\mvaddudm\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvadduwm\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvadduhm\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvaddubm\M} 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/pr119702-2.c b/gcc/testsuite/gcc.target/powerpc/pr119702-2.c
new file mode 100644
index 00000000000..f1c1b8b86e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr119702-2.c
@@ -0,0 +1,53 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+#include <inttypes.h>
+
+void lshift1_64(uint64_t *a) {
+  a[0] *= 2;
+  a[1] *= 2;
+}
+
+void lshift1_32(unsigned int *a) {
+  a[0] *= 2;
+  a[1] *= 2;
+  a[2] *= 2;
+  a[3] *= 2;
+}
+
+void lshift1_16(uint16_t *a) {
+  a[0] *= 2;
+  a[1] *= 2;
+  a[2] *= 2;
+  a[3] *= 2;
+  a[4] *= 2;
+  a[5] *= 2;
+  a[6] *= 2;
+  a[7] *= 2;
+}
+
+void lshift1_8(uint8_t *a) {
+  a[0] *= 2;
+  a[1] *= 2;
+  a[2] *= 2;
+  a[3] *= 2;
+  a[4] *= 2;
+  a[5] *= 2;
+  a[6] *= 2;
+  a[7] *= 2;
+  a[8] *= 2;
+  a[9] *= 2;
+  a[10] *= 2;
+  a[11] *= 2;
+  a[12] *= 2;
+  a[13] *= 2;
+  a[14] *= 2;
+  a[15] *= 2;
+}
+
+
+/* { dg-final { scan-assembler-times {\mvaddudm\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvadduwm\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvadduhm\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvaddubm\M} 1 } } */
+