diff mbox series

aarch64: arm: testsuite: Enable vld1xN and vst1xN tests [PR71233]

Message ID 20250311162136.962448-1-christophe.lyon@linaro.org
State New
Headers
Series aarch64: arm: testsuite: Enable vld1xN and vst1xN tests [PR71233] |

Commit Message

Christophe Lyon March 11, 2025, 4:21 p.m. UTC 
  r14-7202-gc8ec3e1327cb1e added vld1xN and vst1xN intrinsics and some
tests on arm, but didn't enable some existing tests.

Since these tests are shared with aarch64, this patch replaces the
'dg-skip-if "unimplemented" { arm*-*-* }' directives with:
dg-require-effective-target arm_neon_ok { target arm*-*-* }
dg-add-options arm_neon

so that we add the options needed on arm only when targeting arm.

float16 intrinsics would require neon-fp16 FPU, poly64 intrinsics
would require crypto-neon-fp-armv8: the patch enables the
corresponding tests on aarch64 only, since they are already covered by
other tests in gcc.target/arm/simd/.  For some reason, poly64 tests
where missing from x2 and x3 tests, so the patch adds them as needed.

Tested on aarch64-linux-gnu (no change) and arm-linux-gnueabihf (the
additional tests pass).

gcc/testsuite/
	PR target/71233
	* gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: Enable on arm.
	* gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: Likewise.
---
 .../gcc.target/aarch64/advsimd-intrinsics/vld1x2.c  | 11 ++++++++---
 .../gcc.target/aarch64/advsimd-intrinsics/vld1x3.c  | 11 ++++++++---
 .../gcc.target/aarch64/advsimd-intrinsics/vld1x4.c  | 13 ++++++++-----
 .../gcc.target/aarch64/advsimd-intrinsics/vst1x2.c  | 11 ++++++++---
 .../gcc.target/aarch64/advsimd-intrinsics/vst1x3.c  | 11 ++++++++---
 .../gcc.target/aarch64/advsimd-intrinsics/vst1x4.c  | 13 ++++++++-----
 6 files changed, 48 insertions(+), 22 deletions(-)

Comments

Christophe Lyon March 13, 2025, 8:24 p.m. UTC | #1 
On Tue, 11 Mar 2025 at 17:21, Christophe Lyon
<christophe.lyon@linaro.org> wrote:
>
> r14-7202-gc8ec3e1327cb1e added vld1xN and vst1xN intrinsics and some
> tests on arm, but didn't enable some existing tests.
>
> Since these tests are shared with aarch64, this patch replaces the
> 'dg-skip-if "unimplemented" { arm*-*-* }' directives with:
> dg-require-effective-target arm_neon_ok { target arm*-*-* }
> dg-add-options arm_neon
>
> so that we add the options needed on arm only when targeting arm.
>
> float16 intrinsics would require neon-fp16 FPU, poly64 intrinsics
> would require crypto-neon-fp-armv8: the patch enables the
> corresponding tests on aarch64 only, since they are already covered by
> other tests in gcc.target/arm/simd/.  For some reason, poly64 tests
> where missing from x2 and x3 tests, so the patch adds them as needed.
>
> Tested on aarch64-linux-gnu (no change) and arm-linux-gnueabihf (the
> additional tests pass).
>
> gcc/testsuite/
>         PR target/71233
>         * gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: Enable on arm.
>         * gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: Likewise.
>         * gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: Likewise.
>         * gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: Likewise.
>         * gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: Likewise.
>         * gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: Likewise.
> ---
>  .../gcc.target/aarch64/advsimd-intrinsics/vld1x2.c  | 11 ++++++++---
>  .../gcc.target/aarch64/advsimd-intrinsics/vld1x3.c  | 11 ++++++++---
>  .../gcc.target/aarch64/advsimd-intrinsics/vld1x4.c  | 13 ++++++++-----
>  .../gcc.target/aarch64/advsimd-intrinsics/vst1x2.c  | 11 ++++++++---
>  .../gcc.target/aarch64/advsimd-intrinsics/vst1x3.c  | 11 ++++++++---
>  .../gcc.target/aarch64/advsimd-intrinsics/vst1x4.c  | 13 ++++++++-----
>  6 files changed, 48 insertions(+), 22 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
> index 6e56ff171f8..bc2aad09a9c 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
> @@ -1,7 +1,8 @@
>  /* We haven't implemented these intrinsics for arm yet.  */
>  /* { dg-do run } */
> -/* { dg-skip-if "unimplemented" { arm*-*-* } } */
>  /* { dg-options "-O3" } */
> +/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
> +/* { dg-add-options arm_neon } */

Sorry, this does not work when we run the tests with flags setting
arch/cpu to M-profile without multilib.

For instance, if we force:
-mthumb -march=armv8-m.main+dsp+fp -mtune=cortex-m33 -mfloat-abi=hard -mfpu=auto
on a toolchain configured using:
--disable-multilib --with-mode=thumb --with-cpu=cortex-m33 --with-float=hard
arm_neon_ok computes that it needs to add:
-mfpu=neon -mfloat-abi=softfp -mcpu=unset -march=armv7-a
but we fail to link the testcase because we do not have crt0/libs in
softfp mode).

Sigh :-)

Christophe


>
>  #include <arm_neon.h>
>  #include "arm-neon-ref.h"
> @@ -40,7 +41,6 @@ VARIANT (int32, 2, _s32)      \
>  VARIANT (int64, 1, _s64)       \
>  VARIANT (poly8, 8, _p8)                \
>  VARIANT (poly16, 4, _p16)      \
> -VARIANT (float16, 4, _f16)     \
>  VARIANT (float32, 2, _f32)     \
>  VARIANT (uint8, 16, q_u8)      \
>  VARIANT (uint16, 8, q_u16)     \
> @@ -52,11 +52,16 @@ VARIANT (int32, 4, q_s32)   \
>  VARIANT (int64, 2, q_s64)      \
>  VARIANT (poly8, 16, q_p8)      \
>  VARIANT (poly16, 8, q_p16)     \
> -VARIANT (float16, 8, q_f16)    \
>  VARIANT (float32, 4, q_f32)
>
> +/* On arm, poly64 and float16 have dedicated tests
> +   (gcc.target/arm/simd/vld1*) */
>  #ifdef __aarch64__
>  #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)  \
> +VARIANT (poly64, 1, _p64)                      \
> +VARIANT (poly64, 2, q_p64)                     \
> +VARIANT (float16, 4, _f16)                     \
> +VARIANT (float16, 8, q_f16)                    \
>  VARIANT (mfloat8, 8, _mf8)                     \
>  VARIANT (mfloat8, 16, q_mf8)                   \
>  VARIANT (float64, 1, _f64)                     \
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
> index 42aeadf1c7d..5b86ed32930 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
> @@ -1,7 +1,8 @@
>  /* We haven't implemented these intrinsics for arm yet.  */
>  /* { dg-do run } */
> -/* { dg-skip-if "unimplemented" { arm*-*-* } } */
>  /* { dg-options "-O3" } */
> +/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
> +/* { dg-add-options arm_neon } */
>
>  #include <arm_neon.h>
>  #include "arm-neon-ref.h"
> @@ -41,7 +42,6 @@ VARIANT (int32, 2, _s32)      \
>  VARIANT (int64, 1, _s64)       \
>  VARIANT (poly8, 8, _p8)                \
>  VARIANT (poly16, 4, _p16)      \
> -VARIANT (float16, 4, _f16)     \
>  VARIANT (float32, 2, _f32)     \
>  VARIANT (uint8, 16, q_u8)      \
>  VARIANT (uint16, 8, q_u16)     \
> @@ -53,11 +53,16 @@ VARIANT (int32, 4, q_s32)   \
>  VARIANT (int64, 2, q_s64)      \
>  VARIANT (poly8, 16, q_p8)      \
>  VARIANT (poly16, 8, q_p16)     \
> -VARIANT (float16, 8, q_f16)    \
>  VARIANT (float32, 4, q_f32)
>
> +/* On arm, poly64 and float16 have dedicated tests
> +   (gcc.target/arm/simd/vld1*) */
>  #ifdef __aarch64__
>  #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)  \
> +VARIANT (poly64, 1, _p64)                      \
> +VARIANT (poly64, 2, q_p64)                     \
> +VARIANT (float16, 4, _f16)                     \
> +VARIANT (float16, 8, q_f16)                    \
>  VARIANT (mfloat8, 8, _mf8)                     \
>  VARIANT (mfloat8, 16, q_mf8)                   \
>  VARIANT (float64, 1, _f64)                     \
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
> index 694fda86e72..39363a27e5f 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
> @@ -1,7 +1,8 @@
>  /* We haven't implemented these intrinsics for arm yet.  */
>  /* { dg-do run } */
> -/* { dg-skip-if "unimplemented" { arm*-*-* } } */
>  /* { dg-options "-O3" } */
> +/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
> +/* { dg-add-options arm_neon } */
>
>  #include <stdbool.h>
>  #include <arm_neon.h>
> @@ -43,8 +44,6 @@ VARIANT (int32, 2, _s32)      \
>  VARIANT (int64, 1, _s64)       \
>  VARIANT (poly8, 8, _p8)                \
>  VARIANT (poly16, 4, _p16)      \
> -VARIANT (poly64, 1, _p64)      \
> -VARIANT (float16, 4, _f16)     \
>  VARIANT (float32, 2, _f32)     \
>  VARIANT (uint8, 16, q_u8)      \
>  VARIANT (uint16, 8, q_u16)     \
> @@ -56,12 +55,16 @@ VARIANT (int32, 4, q_s32)   \
>  VARIANT (int64, 2, q_s64)      \
>  VARIANT (poly8, 16, q_p8)      \
>  VARIANT (poly16, 8, q_p16)     \
> -VARIANT (poly64, 2, q_p64)     \
> -VARIANT (float16, 8, q_f16)    \
>  VARIANT (float32, 4, q_f32)
>
> +/* On arm, poly64 and float16 have dedicated tests
> +   (gcc.target/arm/simd/vld1*) */
>  #ifdef __aarch64__
>  #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)  \
> +VARIANT (poly64, 1, _p64)                      \
> +VARIANT (poly64, 2, q_p64)                     \
> +VARIANT (float16, 4, _f16)                     \
> +VARIANT (float16, 8, q_f16)                    \
>  VARIANT (mfloat8, 8, _mf8)                     \
>  VARIANT (mfloat8, 16, q_mf8)                   \
>  VARIANT (float64, 1, _f64)                     \
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
> index 69be40a444a..357f381ed96 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
> @@ -1,7 +1,8 @@
>  /* We haven't implemented these intrinsics for arm yet.  */
>  /* { dg-do run } */
> -/* { dg-skip-if "unimplemented" { arm*-*-* } } */
>  /* { dg-options "-O3" } */
> +/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
> +/* { dg-add-options arm_neon } */
>
>  #include <arm_neon.h>
>  #include "arm-neon-ref.h"
> @@ -40,7 +41,6 @@ VARIANT (int32, 2, _s32)      \
>  VARIANT (int64, 1, _s64)       \
>  VARIANT (poly8, 8, _p8)                \
>  VARIANT (poly16, 4, _p16)      \
> -VARIANT (float16, 4, _f16)     \
>  VARIANT (float32, 2, _f32)     \
>  VARIANT (uint8, 16, q_u8)      \
>  VARIANT (uint16, 8, q_u16)     \
> @@ -52,11 +52,16 @@ VARIANT (int32, 4, q_s32)   \
>  VARIANT (int64, 2, q_s64)      \
>  VARIANT (poly8, 16, q_p8)      \
>  VARIANT (poly16, 8, q_p16)     \
> -VARIANT (float16, 8, q_f16)    \
>  VARIANT (float32, 4, q_f32)
>
> +/* On arm, poly64 and float16 have dedicated tests
> +   (gcc.target/arm/simd/vst1*) */
>  #ifdef __aarch64__
>  #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)  \
> +VARIANT (poly64, 1, _p64)                      \
> +VARIANT (poly64, 2, q_p64)                     \
> +VARIANT (float16, 4, _f16)                     \
> +VARIANT (float16, 8, q_f16)                    \
>  VARIANT (mfloat8, 8, _mf8)                     \
>  VARIANT (mfloat8, 16, q_mf8)                   \
>  VARIANT (float64, 1, _f64)                     \
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
> index 4d42bccec3c..83e95e90f69 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
> @@ -1,7 +1,8 @@
>  /* We haven't implemented these intrinsics for arm yet.  */
>  /* { dg-do run } */
> -/* { dg-skip-if "unimplemented" { arm*-*-* } } */
>  /* { dg-options "-O3" } */
> +/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
> +/* { dg-add-options arm_neon } */
>
>  #include <arm_neon.h>
>  #include "arm-neon-ref.h"
> @@ -41,7 +42,6 @@ VARIANT (int32, 2, _s32)      \
>  VARIANT (int64, 1, _s64)       \
>  VARIANT (poly8, 8, _p8)                \
>  VARIANT (poly16, 4, _p16)      \
> -VARIANT (float16, 4, _f16)     \
>  VARIANT (float32, 2, _f32)     \
>  VARIANT (uint8, 16, q_u8)      \
>  VARIANT (uint16, 8, q_u16)     \
> @@ -53,11 +53,16 @@ VARIANT (int32, 4, q_s32)   \
>  VARIANT (int64, 2, q_s64)      \
>  VARIANT (poly8, 16, q_p8)      \
>  VARIANT (poly16, 8, q_p16)     \
> -VARIANT (float16, 8, q_f16)    \
>  VARIANT (float32, 4, q_f32)
>
> +/* On arm, poly64 and float16 have dedicated tests
> +   (gcc.target/arm/simd/vst1*) */
>  #ifdef __aarch64__
>  #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)  \
> +VARIANT (poly64, 1, _p64)                      \
> +VARIANT (poly64, 2, q_p64)                     \
> +VARIANT (float16, 4, _f16)                     \
> +VARIANT (float16, 8, q_f16)                    \
>  VARIANT (mfloat8, 8, _mf8)                     \
>  VARIANT (mfloat8, 16, q_mf8)                   \
>  VARIANT (float64, 1, _f64)                     \
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
> index ddc7fa59465..ce8bf93a58b 100644
> --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
> @@ -1,7 +1,8 @@
>  /* We haven't implemented these intrinsics for arm yet.  */
>  /* { dg-do run } */
> -/* { dg-skip-if "unimplemented" { arm*-*-* } } */
>  /* { dg-options "-O3" } */
> +/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
> +/* { dg-add-options arm_neon } */
>
>  #include <arm_neon.h>
>  #include "arm-neon-ref.h"
> @@ -42,8 +43,6 @@ VARIANT (int32, 2, _s32)      \
>  VARIANT (int64, 1, _s64)       \
>  VARIANT (poly8, 8, _p8)                \
>  VARIANT (poly16, 4, _p16)      \
> -VARIANT (poly64, 1, _p64)      \
> -VARIANT (float16, 4, _f16)     \
>  VARIANT (float32, 2, _f32)     \
>  VARIANT (uint8, 16, q_u8)      \
>  VARIANT (uint16, 8, q_u16)     \
> @@ -55,12 +54,16 @@ VARIANT (int32, 4, q_s32)   \
>  VARIANT (int64, 2, q_s64)      \
>  VARIANT (poly8, 16, q_p8)      \
>  VARIANT (poly16, 8, q_p16)     \
> -VARIANT (poly64, 2, q_p64)     \
> -VARIANT (float16, 8, q_f16)    \
>  VARIANT (float32, 4, q_f32)
>
> +/* On arm, poly64 and float16 have dedicated tests
> +   (gcc.target/arm/simd/vst1*) */
>  #ifdef __aarch64__
>  #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)  \
> +VARIANT (poly64, 1, _p64)                      \
> +VARIANT (poly64, 2, q_p64)                     \
> +VARIANT (float16, 4, _f16)                     \
> +VARIANT (float16, 8, q_f16)                    \
>  VARIANT (mfloat8, 8, _mf8)                     \
>  VARIANT (mfloat8, 16, q_mf8)                   \
>  VARIANT (float64, 1, _f64)                     \
> --
> 2.34.1
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
index 6e56ff171f8..bc2aad09a9c 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x2.c
@@ -1,7 +1,8 @@ 
 /* We haven't implemented these intrinsics for arm yet.  */
 /* { dg-do run } */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
 /* { dg-options "-O3" } */
+/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
+/* { dg-add-options arm_neon } */
 
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
@@ -40,7 +41,6 @@  VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -52,11 +52,16 @@  VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+/* On arm, poly64 and float16 have dedicated tests
+   (gcc.target/arm/simd/vld1*) */
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
+VARIANT (float16, 4, _f16)			\
+VARIANT (float16, 8, q_f16)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
index 42aeadf1c7d..5b86ed32930 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x3.c
@@ -1,7 +1,8 @@ 
 /* We haven't implemented these intrinsics for arm yet.  */
 /* { dg-do run } */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
 /* { dg-options "-O3" } */
+/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
+/* { dg-add-options arm_neon } */
 
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
@@ -41,7 +42,6 @@  VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -53,11 +53,16 @@  VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+/* On arm, poly64 and float16 have dedicated tests
+   (gcc.target/arm/simd/vld1*) */
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
+VARIANT (float16, 4, _f16)			\
+VARIANT (float16, 8, q_f16)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
index 694fda86e72..39363a27e5f 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld1x4.c
@@ -1,7 +1,8 @@ 
 /* We haven't implemented these intrinsics for arm yet.  */
 /* { dg-do run } */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
 /* { dg-options "-O3" } */
+/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
+/* { dg-add-options arm_neon } */
 
 #include <stdbool.h>
 #include <arm_neon.h>
@@ -43,8 +44,6 @@  VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (poly64, 1, _p64)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -56,12 +55,16 @@  VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (poly64, 2, q_p64)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+/* On arm, poly64 and float16 have dedicated tests
+   (gcc.target/arm/simd/vld1*) */
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
+VARIANT (float16, 4, _f16)			\
+VARIANT (float16, 8, q_f16)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
index 69be40a444a..357f381ed96 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x2.c
@@ -1,7 +1,8 @@ 
 /* We haven't implemented these intrinsics for arm yet.  */
 /* { dg-do run } */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
 /* { dg-options "-O3" } */
+/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
+/* { dg-add-options arm_neon } */
 
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
@@ -40,7 +41,6 @@  VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -52,11 +52,16 @@  VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+/* On arm, poly64 and float16 have dedicated tests
+   (gcc.target/arm/simd/vst1*) */
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
+VARIANT (float16, 4, _f16)			\
+VARIANT (float16, 8, q_f16)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
index 4d42bccec3c..83e95e90f69 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x3.c
@@ -1,7 +1,8 @@ 
 /* We haven't implemented these intrinsics for arm yet.  */
 /* { dg-do run } */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
 /* { dg-options "-O3" } */
+/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
+/* { dg-add-options arm_neon } */
 
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
@@ -41,7 +42,6 @@  VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -53,11 +53,16 @@  VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+/* On arm, poly64 and float16 have dedicated tests
+   (gcc.target/arm/simd/vst1*) */
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
+VARIANT (float16, 4, _f16)			\
+VARIANT (float16, 8, q_f16)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
index ddc7fa59465..ce8bf93a58b 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst1x4.c
@@ -1,7 +1,8 @@ 
 /* We haven't implemented these intrinsics for arm yet.  */
 /* { dg-do run } */
-/* { dg-skip-if "unimplemented" { arm*-*-* } } */
 /* { dg-options "-O3" } */
+/* { dg-require-effective-target arm_neon_ok { target arm*-*-* } } */
+/* { dg-add-options arm_neon } */
 
 #include <arm_neon.h>
 #include "arm-neon-ref.h"
@@ -42,8 +43,6 @@  VARIANT (int32, 2, _s32)	\
 VARIANT (int64, 1, _s64)	\
 VARIANT (poly8, 8, _p8)		\
 VARIANT (poly16, 4, _p16)	\
-VARIANT (poly64, 1, _p64)	\
-VARIANT (float16, 4, _f16)	\
 VARIANT (float32, 2, _f32)	\
 VARIANT (uint8, 16, q_u8)	\
 VARIANT (uint16, 8, q_u16)	\
@@ -55,12 +54,16 @@  VARIANT (int32, 4, q_s32)	\
 VARIANT (int64, 2, q_s64)	\
 VARIANT (poly8, 16, q_p8)	\
 VARIANT (poly16, 8, q_p16)	\
-VARIANT (poly64, 2, q_p64)	\
-VARIANT (float16, 8, q_f16)	\
 VARIANT (float32, 4, q_f32)
 
+/* On arm, poly64 and float16 have dedicated tests
+   (gcc.target/arm/simd/vst1*) */
 #ifdef __aarch64__
 #define VARIANTS(VARIANT) VARIANTS_1(VARIANT)	\
+VARIANT (poly64, 1, _p64)			\
+VARIANT (poly64, 2, q_p64)			\
+VARIANT (float16, 4, _f16)			\
+VARIANT (float16, 8, q_f16)			\
 VARIANT (mfloat8, 8, _mf8)			\
 VARIANT (mfloat8, 16, q_mf8)			\
 VARIANT (float64, 1, _f64)			\