From patchwork Mon Feb 10 05:43:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 106221 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3195C385840D for ; Mon, 10 Feb 2025 05:49:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3195C385840D Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=TruCCXYI X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) by sourceware.org (Postfix) with ESMTPS id A4FD13858CDA for ; Mon, 10 Feb 2025 05:43:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A4FD13858CDA Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A4FD13858CDA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1739166207; cv=none; b=ll26MwId7hQjPF5NC+OCt02AZ99NacY2mUHJXrE3pLCBZaa9V3NgLwlfd72YNoiGUzLOkBaYkar4BdKohYa4+uJ3Gr+6YvmMLr5KnsexWWwPFZtn7ODbXNr8UusixEfl5g+4NApGON021w9Sw4VMHQBMAgmiTpv30/DW21ER1OQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1739166207; c=relaxed/simple; bh=fNIqNUilre9BC6yE+EkC1ut1SWK7FYoDRnXQeqpzKng=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=qRTUMJO/9NYr5nP3l0dp3/pKXWAEtl5y88VD15HtaGVhB6QmofqZFdE7vTMcZbH2WuaKvPS6KR+ZwQ+KF71MaMuwuSEd/cco8SqEgw+7z7mEbzp/K9ScaCm8kJXgzD8HY6/XWsNb6+4DOJt822VZ9p+x08Feg9APL+Qd+5VdEPY= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A4FD13858CDA DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739166208; x=1770702208; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fNIqNUilre9BC6yE+EkC1ut1SWK7FYoDRnXQeqpzKng=; b=TruCCXYIB0W4Y4M0KKJmH1FzA+giFUTxuAGh7bmIEpboZMjfRzXuob0J Bs9Cb3xMmBGedMIgAK1eUJ3crG5KbZWDG4p9Kl2Jg0B/AQT/SpTuZfwtZ oDrzNW/n0SySD+gzt+gtCpRvNE77qGm5gOedQX+nr9T3GIgTi+iM2q4lz 3Bibe41j5uPS1HrnEook3pgKz1qIZqYXjqWaxaquxSYx18h14IIjC57mp foQ4akWv/pSz//Sou6f3dQEVRMVSYJgwJWPFrCep+glFBuxywR45JqZLD nycqfx2RlsldGAvR9PuvlaXcujhrY08mEGXEyG+UF2j6GXmSzyseM/M4L w==; X-CSE-ConnectionGUID: E7sLXvxSTrSpz6JTcrFNvg== X-CSE-MsgGUID: /sSyU5DVQLGN1xV5jaRyvg== X-IronPort-AV: E=McAfee;i="6700,10204,11340"; a="49968388" X-IronPort-AV: E=Sophos;i="6.13,273,1732608000"; d="scan'208";a="49968388" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2025 21:43:21 -0800 X-CSE-ConnectionGUID: cUMjfoxJRLCOs6pMxmD4+A== X-CSE-MsgGUID: ooAWAK2qRW22x9Q1hXNEHw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,273,1732608000"; d="scan'208";a="112016229" Received: from scymds04.sc.intel.com ([10.82.73.238]) by fmviesa007.fm.intel.com with ESMTP; 09 Feb 2025 21:43:21 -0800 Received: from jfel-spr-6155.jf.intel.com (jfel-spr-6155.jf.intel.com [10.7.183.102]) by scymds04.sc.intel.com (Postfix) with ESMTP id 694B72003AE0; Sun, 9 Feb 2025 21:43:20 -0800 (PST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com Subject: [PATCH 1/3] Use NO_REGS in cost calculation when the preferred register class are not known yet. Date: Sun, 9 Feb 2025 21:43:18 -0800 Message-Id: <20250210054320.1014838-2-hongtao.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250210054320.1014838-1-hongtao.liu@intel.com> References: <20250210054320.1014838-1-hongtao.liu@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org gcc/ChangeLog: PR rtl-optimization/108707 * ira-costs.cc (scan_one_insn): Use NO_REGS instead of GENERAL_REGS when preferred reg_class is not known. gcc/testsuite/ChangeLog: * gcc.target/i386/pr108707.c: New test. (cherry picked from commit 0368d169492017cfab5622d38b15be94154d458c) --- gcc/ira-costs.cc | 5 ++++- gcc/testsuite/gcc.target/i386/pr108707.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr108707.c diff --git a/gcc/ira-costs.cc b/gcc/ira-costs.cc index bdb1356af91..003963f2a19 100644 --- a/gcc/ira-costs.cc +++ b/gcc/ira-costs.cc @@ -1572,7 +1572,10 @@ scan_one_insn (rtx_insn *insn) && (! ira_use_lra_p || ! pic_offset_table_rtx || ! contains_symbol_ref_p (XEXP (note, 0)))) { - enum reg_class cl = GENERAL_REGS; + /* Costs for NO_REGS are used in cost calculation on the + 1st pass when the preferred register classes are not + known yet. In this case we take the best scenario. */ + enum reg_class cl = NO_REGS; rtx reg = SET_DEST (set); int num = COST_INDEX (REGNO (reg)); diff --git a/gcc/testsuite/gcc.target/i386/pr108707.c b/gcc/testsuite/gcc.target/i386/pr108707.c new file mode 100644 index 00000000000..6405cfe7cdc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr108707.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-not {(?n)vfmadd[1-3]*ps.*\(} { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler-times {(?n)vfmadd[1-3]*ps[ \t]*} 3 } } */ + +#include + +void +foo (__m512 pv, __m512 a, __m512 b, __m512 c, + __m512* pdest, __m512* p1) +{ + __m512 t = *p1; + pdest[0] = _mm512_fmadd_ps (t, pv, a); + pdest[1] = _mm512_fmadd_ps (t, pv, b); + pdest[2] = _mm512_fmadd_ps (t, pv, c); +}