[53/61] Inefficient scattered double precision load in MSA

Message ID 20250131171232.1018281-55-aleksandar.rakic@htecgroup.com
State New
Headers
Series Improve Mips target |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm fail Patch failed to apply
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 fail Patch failed to apply

Commit Message

Aleksandar Rakic Jan. 31, 2025, 5:13 p.m. UTC
  From: Mihailo Stojanovic <mihailo.stojanovic@rt-rk.com>

gcc/
	* config/mips/mips.cc (mips_legitimate_combined_insn):
	New function.

Cherry-picked 092a39db956a418e7e020107b062c170ed976841
from https://github.com/MIPS/gcc

Signed-off-by: Mihailo Stojanovic <mistojanovic@wavecomp.com>
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 gcc/config/mips/mips.cc | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
  

Patch

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 20128c7f537..4894e07f72c 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -25749,6 +25749,22 @@  mips_set_up_by_prologue (hard_reg_set_container *regs)
     CLEAR_HARD_REG_BIT (regs->set, GLOBAL_POINTER_REGNUM);
 }
 
+/* Implemet TARGET_LEGITIMATE_COMBINED_INSN hook.  */
+
+static bool
+mips_legitimate_combined_insn (rtx_insn *insn)
+{
+  rtx p = PATTERN (insn);
+  if (GET_CODE (p) == SET
+      && GET_CODE (XEXP (p, 1)) == VEC_DUPLICATE
+      && GET_CODE (XEXP (XEXP (p, 1), 0)) == REG
+      && (GET_MODE_UNIT_SIZE (GET_MODE (XEXP (XEXP (p, 1), 0)))
+	  > UNITS_PER_WORD))
+    return false;
+
+  return true;
+}
+
 void
 mips_bit_clear_info (enum machine_mode mode, unsigned HOST_WIDE_INT m,
 		      int *start_pos, int *size)
@@ -26130,6 +26146,9 @@  mips_noce_conversion_profitable_p (rtx_insn *seq, struct noce_if_info *if_info)
 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
 
+#undef TARGET_LEGITIMATE_COMBINED_INSN
+#define TARGET_LEGITIMATE_COMBINED_INSN mips_legitimate_combined_insn
+
 #undef TARGET_HARD_REGNO_SCRATCH_OK
 #define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok