[51/61] Test solution on dspmac builtins

Message ID 20250131171232.1018281-53-aleksandar.rakic@htecgroup.com
State New
Headers
Series Improve Mips target |

Commit Message

Aleksandar Rakic Jan. 31, 2025, 5:13 p.m. UTC
  From: Mihailo Stojanovic <mistojanovic@wavecomp.com>

gcc/

    * config/mips/mips.cc (mips_expand_builtin_insn): During expansion
    of DSP mac builtins, force the operands which correspond to the same
    inout register to have the same pseudo assigned.

gcc/testsuite

    * gcc.target/mips/mac_zero_reload.c: New testcase.

Cherry-picked 110ec7a3e56737bb8ed2ae653298aa55ad014377
and 712169a3630d45284ddd6ea6d0dedcb2b60e0ba4
from https://github.com/MIPS/gcc

Signed-off-by: Mihailo Stojanovic <mistojanovic@wavecomp.com>
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 gcc/config/mips/mips.cc                       | 24 ++++++++++++++
 .../gcc.target/mips/mac_zero_reload.c         | 32 +++++++++++++++++++
 2 files changed, 56 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/mac_zero_reload.c
  

Patch

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index fa2039175ff..20128c7f537 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -19215,6 +19215,30 @@  mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
     case CODE_FOR_msa_dpsub_u_w:
     case CODE_FOR_msa_dpsub_u_h:
     case CODE_FOR_msa_dpsub_u_d:
+
+    case CODE_FOR_mips_dpau_h_qbl:
+    case CODE_FOR_mips_dpau_h_qbr:
+    case CODE_FOR_mips_dpsu_h_qbl:
+    case CODE_FOR_mips_dpsu_h_qbr:
+    case CODE_FOR_mips_dpaq_s_w_ph:
+    case CODE_FOR_mips_dpsq_s_w_ph:
+    case CODE_FOR_mips_mulsaq_s_w_ph:
+    case CODE_FOR_mips_dpaq_sa_l_w:
+    case CODE_FOR_mips_dpsq_sa_l_w:
+    case CODE_FOR_mips_maq_s_w_phl:
+    case CODE_FOR_mips_maq_s_w_phr:
+    case CODE_FOR_mips_maq_sa_w_phl:
+    case CODE_FOR_mips_maq_sa_w_phr:
+
+    case CODE_FOR_mips_dpa_w_ph:
+    case CODE_FOR_mips_dps_w_ph:
+    case CODE_FOR_mips_mulsa_w_ph:
+    case CODE_FOR_mips_dpax_w_ph:
+    case CODE_FOR_mips_dpsx_w_ph:
+    case CODE_FOR_mips_dpaqx_s_w_ph:
+    case CODE_FOR_mips_dpaqx_sa_w_ph:
+    case CODE_FOR_mips_dpsqx_s_w_ph:
+    case CODE_FOR_mips_dpsqx_sa_w_ph:
       /* Force the operands which correspond to the same in-out register
 	  to have the same pseudo assigned to them.  If the input operand
 	  is not REG, create one for it.  */
diff --git a/gcc/testsuite/gcc.target/mips/mac_zero_reload.c b/gcc/testsuite/gcc.target/mips/mac_zero_reload.c
new file mode 100644
index 00000000000..63261bc1493
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/mac_zero_reload.c
@@ -0,0 +1,32 @@ 
+/* { dg-do compile } */
+/* { dg-options "-fno-unroll-loops -mgp32 -mdspr2" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+/* { dg-final { scan-assembler-not "\tmflo\t" } } */
+/* { dg-final { scan-assembler-not "\tmfhi\t" } } */
+/* { dg-final { scan-assembler-not "\tmtlo\t" } } */
+/* { dg-final { scan-assembler-not "\tmthi\t" } } */
+
+typedef short v2i16 __attribute__ ((vector_size(4)));
+
+extern v2i16 ps32Ptrl[4096];
+
+extern int sink[4096];
+
+int main(void)
+{
+    v2i16 v2i16_h0;
+    long long   s64Acc;
+
+    for (int i = 0; i < 4; ++i)
+    {
+        v2i16_h0 = ps32Ptrl[i];
+
+        s64Acc = 0;
+
+        s64Acc = __builtin_mips_dpa_w_ph(s64Acc, v2i16_h0, v2i16_h0);
+
+        sink[i] = __builtin_mips_extr_rs_w(s64Acc, 0);
+    }
+
+    return 0;
+}