diff mbox series

[29/61] Prevent FP values being spilled to GPRs

Message ID 20250131171232.1018281-31-aleksandar.rakic@htecgroup.com
State New
Headers
Series Improve Mips target |

Commit Message

Aleksandar Rakic Jan. 31, 2025, 5:13 p.m. UTC 
  From: Simon Dardis <simon.dardis@imgtec.com>

gcc/
	* config/mips/mips.cc (mips_ira_change_pseudo_allocno_class):
	Prevent FP modes being reloaded to GPRs. Don't force integer
	mode pseudos into GR_REGS (and likewise for float mode pseudos
	and FP_REGS) if both the allocno class and best cost class are
	ALL_REGS to prevent inefficient scattered complex<float> load
	with MSA.

gcc/testsuite/

    * gcc.target/mips/msa-scattered-load.c: New.

Cherry-picked 1996aa906aeb4f958b77bb12aa60745ca9962fa2,
5314c36e83e9f8e13144b3a991e392d152514938 and
e9b42ac26ee8eeea0f5ca5a54b3b2dca5a69dd71
from https://github.com/MIPS/gcc

Signed-off-by: Simon Dardis <simon.dardis@imgtec.com>
Signed-off-by: Mihailo Stojanovic <mistojanovic@wavecomp.com>
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
---
 gcc/config/mips/mips.cc                       | 16 ++++++++++++---
 .../gcc.target/mips/msa-scattered-load.c      | 20 +++++++++++++++++++
 2 files changed, 33 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/msa-scattered-load.c
diff mbox series

Patch

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 36ce297085b..1fa727c2ff5 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -25347,7 +25347,7 @@  mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
 
 static reg_class_t
 mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,
-				      reg_class_t best_class ATTRIBUTE_UNUSED)
+				      reg_class_t best_class)
 {
   /* LRA will allocate an FPR for an integer mode pseudo instead of spilling
      to memory if an FPR is present in the allocno class.  It is rare that
@@ -25357,7 +25357,9 @@  mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,
      to reload into FPRs in LRA.  Such reloads are sometimes eliminated and
      sometimes only partially eliminated.  We choose to take this penalty
      in order to eliminate usage of FPRs in code that does not use floating
-     point data.
+     point data.  In the case when IRA computes both allocno class and best
+     cost class as ALL_REGS, do not force integer mode pseudo into GR_REGS
+     as it is probably best to be placed into FPR.
 
      This change has a similar effect to increasing the cost of FPR->GPR
      register moves for integer modes so that they are higher than the cost
@@ -25366,8 +25368,16 @@  mips_ira_change_pseudo_allocno_class (int regno, reg_class_t allocno_class,
      This is also similar to forbidding integer mode values in FPRs entirely
      but this would lead to an inconsistency in the integer to/from float
      instructions that say integer mode values must be placed in FPRs.  */
-  if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS)
+  if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS
+      && allocno_class != best_class)
     return GR_REGS;
+
+  /* Likewise for the mirror case of floating mode pseudos being allocated in
+     a GPR.  */
+  if (FLOAT_MODE_P (PSEUDO_REGNO_MODE (regno)) && allocno_class == ALL_REGS
+      && allocno_class != best_class)
+    return FP_REGS;
+
   return allocno_class;
 }
 
diff --git a/gcc/testsuite/gcc.target/mips/msa-scattered-load.c b/gcc/testsuite/gcc.target/mips/msa-scattered-load.c
new file mode 100644
index 00000000000..f42574ae772
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-scattered-load.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mfp64 -mhard-float -mmsa" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+#include <msa.h>
+#include <stddef.h>
+#include <complex.h>
+
+void pgather2cf1(const float complex* from, v4f32* pv, size_t stride) {
+  v4f32 v;
+  v[0] = crealf(from[0]);
+  v[1] = cimagf(from[0]);
+  v[2] = crealf(from[stride]);
+  v[3] = cimagf(from[stride]);
+  *pv = v;
+}
+
+/* { dg-final { scan-assembler-not "mfc1" } } */
+/* { dg-final { scan-assembler-not "mtc1" } } */
+