diff mbox series

MIPS: Add conditions for use of the -mmips16e2 and -mips16 option.

Message ID 20250116020542.2591277-1-jie.mei@oss.cipunited.com
State New
Headers
Series MIPS: Add conditions for use of the -mmips16e2 and -mips16 option. |

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Commit Message

Jie Mei Jan. 16, 2025, 2:05 a.m. UTC 
  MIPS16e2 ASE is a superset of MIPS16e ASE, which is again a superset
of MIPS16 ASE. Later, all of them are forbidden in Release 6.

Make -mmips16e2 imply -mips16 as the ASE requires, so users won't
be surprised even if they expect it to. Meanwhile, check if
mips_isa_rev <= 5 when -mips16 is effective and >= 1 when -mmips16e2
is effective.

gcc/ChangeLog:
	* config/mips/mips.cc(mips_option_override):Add conditions
	for use of the -mmips16e2 and -mips16 option.

gcc/testsuite/ChangeLog:
	* gcc.target/mips/mips16e2-cache.c: Use isa_rev>=1 instead of
	-mips32r2 and remove -mips16 option.
	* gcc.target/mips/mips16e2-cmov.c: Add isa_rev>=1 and remove
	-mips16 option.
	* gcc.target/mips/mips16e2-gp.c: Same as above.
	* gcc.target/mips/mips16e2.c: Same as above.

Co-developed-by: Rong Zhang <rongrong@oss.cipunited.com>
Signed-off-by: Rong Zhang <rongrong@oss.cipunited.com>
---
 gcc/config/mips/mips.cc                       | 19 +++++++++++++++++++
 .../gcc.target/mips/mips16e2-cache.c          |  2 +-
 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c |  2 +-
 gcc/testsuite/gcc.target/mips/mips16e2-gp.c   |  2 +-
 gcc/testsuite/gcc.target/mips/mips16e2.c      |  2 +-
 5 files changed, 23 insertions(+), 4 deletions(-)

Comments

Maciej W. Rozycki Jan. 16, 2025, 11:41 a.m. UTC | #1 
On Thu, 16 Jan 2025, Jie Mei wrote:

> Make -mmips16e2 imply -mips16 as the ASE requires, so users won't
> be surprised even if they expect it to. Meanwhile, check if
> mips_isa_rev <= 5 when -mips16 is effective and >= 1 when -mmips16e2
> is effective.

 MIPSr1 is incompatible with MIPS16e2, and the only implementation known 
to me is MIPSr3.

  Maciej
Rong Zhang Jan. 17, 2025, 4:53 a.m. UTC | #2 
On Thu, 2025-01-16 at 11:41 +0000, Maciej W. Rozycki wrote:
> On Thu, 16 Jan 2025, Jie Mei wrote:
> 
> > Make -mmips16e2 imply -mips16 as the ASE requires, so users won't
> > be surprised even if they expect it to. Meanwhile, check if
> > mips_isa_rev <= 5 when -mips16 is effective and >= 1 when -mmips16e2
> > is effective.
> 
>  MIPSr1 is incompatible with MIPS16e2, and the only implementation known 
> to me is MIPSr3.

The revision check adheres to the ASE manual (MIPS16e2 Application-
Specific Extension Technical Reference Manual, MD01172-2B-MIPS16e2-AFP-
01.00):

   1.1 Base Architecture Requirements
   
   The MIPS16e2 ASE requires the following base architecture support:
   
   The MIPS32 or MIPS64 Architecture: The MIPS16e2 ASE requires a
   compliant implementation of the	MIPS32 or MIPS64 Architecture.

That being said, after some brief investigation, I believe you're
right. Some MIPS16e2 instructions do not have MIPS32/64 equivalent
before MIPSr2, so implementing MIPS16e2 upon MIPSr1 is not viable.
Thanks for pointing that out.

Except for the fact that the first implementation of MIPS16e2 is based
on MIPSr3, there seems no blocker for implementing MIPS16e2 upon
MIPSr2. We'll seed a v2 patch raising the minimal revision to r2.

>   Maciej

Thanks,
Rong
diff mbox series

Patch

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 492fa285477..26adc01be33 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -20402,6 +20402,16 @@  mips_option_override (void)
   if (TARGET_MICROMIPS && TARGET_MIPS16)
     error ("unsupported combination: %s", "-mips16 -mmicromips");
 
+  /* Make -mmips16e2 imply -mips16 and forbid its coexistence with
+     -mmicromips as the ASE requires.  */
+  if (TARGET_MIPS16E2)
+  {
+    if (TARGET_MICROMIPS)
+      error ("unsupported combination: %s", "-mmips16e2 -mmicromips");
+
+    target_flags |= MASK_MIPS16;
+  }
+
   /* Prohibit Paired-Single and MSA combination.  This is software restriction
      rather than architectural.  */
   if (ISA_HAS_MSA && TARGET_PAIRED_SINGLE_FLOAT)
@@ -20654,6 +20664,15 @@  mips_option_override (void)
 	      "-mcompact-branches=never");
     }
 
+  /* MIPS16* ASE is forbidden in Release 6, so -mips16 is not available
+     for MIPS R6 onwards.  */
+  if ((mips_base_compression_flags & MASK_MIPS16) && mips_isa_rev >= 6)
+    error ("MIPS16* ASE is forbidden in Release 6");
+
+  /* Make sure that the user use Release[1,5] when using -mmips16e2.  */
+  if (TARGET_MIPS16E2 && mips_isa_rev < 1)
+    error ("%<-mmips16e2%> requires Release[1,5]");
+
   /* Require explicit relocs for MIPS R6 onwards.  This enables simplification
      of the compact branch and jump support through the backend.  */
   if (!TARGET_EXPLICIT_RELOCS && mips_isa_rev >= 6)
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
index dcc39b580f5..aabb27731d7 100644
--- a/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-cache.c
@@ -1,4 +1,4 @@ 
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips32r2 -mips16 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=1 -mmips16e2" } */
 /* { dg-skip-if "naming registers makes this a code quality test" { *-*-* } { "-O0" } { "" } } */
 
 /* Test cache.  */
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
index 129ea23b65b..9e7c52c17af 100644
--- a/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
@@ -1,4 +1,4 @@ 
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2 -mbranch-cost=2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=1 -mmips16e2 -mbranch-cost=2" } */
 /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
 
 /* Test MOVN.  */
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
index 7955472bde3..b067e6be0c6 100644
--- a/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2-gp.c
@@ -1,4 +1,4 @@ 
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=1 -mmips16e2" } */
 /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
  
 /* Generate GP-relative ADDIU.  */
diff --git a/gcc/testsuite/gcc.target/mips/mips16e2.c b/gcc/testsuite/gcc.target/mips/mips16e2.c
index 166aa742268..6f707aed43d 100644
--- a/gcc/testsuite/gcc.target/mips/mips16e2.c
+++ b/gcc/testsuite/gcc.target/mips/mips16e2.c
@@ -1,4 +1,4 @@ 
-/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 -mips16 -mmips16e2" } */
+/* { dg-options "-mno-abicalls -mgpopt -G8 -mabi=32 isa_rev>=1 -mmips16e2" } */
 /* { dg-skip-if "per-function expected output" { *-*-* } { "-flto" } { "" } } */
  
 /* ANDI is a two operand instruction.  Hence, it won't be generated if src and