diff mbox series

LoongArch: Add alsl.wu

Message ID 20250115100926.3172965-2-xry111@xry111.site
State Committed
Commit cc6176a921cbe3b9db323b1cd557efe4f299171a
Headers
Series LoongArch: Add alsl.wu |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-arm success Build passed
linaro-tcwg-bot/tcwg_gcc_check--master-arm success Test passed
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Build passed

Commit Message

Xi Ruoyao Jan. 15, 2025, 10:09 a.m. UTC 
  On 64-bit capable LoongArch hardware, alsl.wu is similar to alsl.w but
zero-extending the 32-bit result.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (alslsi3_extend): Add alsl.wu.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/alsl_wu.c: New test.
---
 gcc/config/loongarch/loongarch.md            | 8 ++++----
 gcc/testsuite/gcc.target/loongarch/alsl_wu.c | 9 +++++++++
 2 files changed, 13 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/alsl_wu.c

Comments

Lulu Cheng Jan. 16, 2025, 11:12 a.m. UTC | #1 
LGTM!

Thanks!

在 2025/1/15 下午6:09, Xi Ruoyao 写道:
> On 64-bit capable LoongArch hardware, alsl.wu is similar to alsl.w but
> zero-extending the 32-bit result.
>
> gcc/ChangeLog:
>
> 	* config/loongarch/loongarch.md (alslsi3_extend): Add alsl.wu.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/loongarch/alsl_wu.c: New test.
> ---
>   gcc/config/loongarch/loongarch.md            | 8 ++++----
>   gcc/testsuite/gcc.target/loongarch/alsl_wu.c | 9 +++++++++
>   2 files changed, 13 insertions(+), 4 deletions(-)
>   create mode 100644 gcc/testsuite/gcc.target/loongarch/alsl_wu.c
>
> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
> index 59f45770311..1b46e8e4af0 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -3143,15 +3143,15 @@ (define_insn "alsl<mode>3"
>     [(set_attr "type" "arith")
>      (set_attr "mode" "<MODE>")])
>   
> -(define_insn "alslsi3_extend"
> +(define_insn "*alslsi3_extend"
>     [(set (match_operand:DI 0 "register_operand" "=r")
> -	(sign_extend:DI
> +	(any_extend:DI
>   	  (plus:SI
>   	    (ashift:SI (match_operand:SI 1 "register_operand" "r")
>   		       (match_operand 2 "const_immalsl_operand" ""))
>   	    (match_operand:SI 3 "register_operand" "r"))))]
> -  ""
> -  "alsl.w\t%0,%1,%3,%2"
> +  "TARGET_64BIT"
> +  "alsl.w<u>\t%0,%1,%3,%2"
>     [(set_attr "type" "arith")
>      (set_attr "mode" "SI")])
>   
> diff --git a/gcc/testsuite/gcc.target/loongarch/alsl_wu.c b/gcc/testsuite/gcc.target/loongarch/alsl_wu.c
> new file mode 100644
> index 00000000000..65f55e629dd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/loongarch/alsl_wu.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=loongarch64 -mabi=lp64d -O2" } */
> +/* { dg-final { scan-assembler "alsl\\.wu" } } */
> +
> +unsigned long
> +test (unsigned int a, unsigned int b)
> +{
> +  return (a << 2) + b;
> +}
diff mbox series

Patch

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 59f45770311..1b46e8e4af0 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -3143,15 +3143,15 @@  (define_insn "alsl<mode>3"
   [(set_attr "type" "arith")
    (set_attr "mode" "<MODE>")])
 
-(define_insn "alslsi3_extend"
+(define_insn "*alslsi3_extend"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(sign_extend:DI
+	(any_extend:DI
 	  (plus:SI
 	    (ashift:SI (match_operand:SI 1 "register_operand" "r")
 		       (match_operand 2 "const_immalsl_operand" ""))
 	    (match_operand:SI 3 "register_operand" "r"))))]
-  ""
-  "alsl.w\t%0,%1,%3,%2"
+  "TARGET_64BIT"
+  "alsl.w<u>\t%0,%1,%3,%2"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
 
diff --git a/gcc/testsuite/gcc.target/loongarch/alsl_wu.c b/gcc/testsuite/gcc.target/loongarch/alsl_wu.c
new file mode 100644
index 00000000000..65f55e629dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/alsl_wu.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2" } */
+/* { dg-final { scan-assembler "alsl\\.wu" } } */
+
+unsigned long
+test (unsigned int a, unsigned int b)
+{
+  return (a << 2) + b;
+}