From patchwork Wed Jan 8 09:02:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong X-Patchwork-Id: 104325 X-Patchwork-Delegate: kito.cheng@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 59DC53858C98 for ; Wed, 8 Jan 2025 09:06:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 59DC53858C98 X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTPS id 7FB9E385800F for ; Wed, 8 Jan 2025 09:03:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7FB9E385800F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7FB9E385800F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1736327003; cv=none; b=PGFr5kljl3tm9tSbeh3Ci6VDau2pgFA0HizTgjwxK8jCTgr5bqEc+ytT72TuokaI0lnTUliywC11YPuI4nGZ5l6EdtmGYJ1lQgN9L6zWOq/mnZubgcImSGUTLhw65DH+n016emQjS8fMc47bP0xjgdDj0pK5K8CQGlPlNO9dcQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1736327003; c=relaxed/simple; bh=hNz9vS1xIxzbk3KSUpq92wp3fQtHn7lqe7QAdyqq05A=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=PDWZRRJ6TSj6cn4NHPxgE8MvVpVBn3thumTyRARcL4sMQEdZ5wZqQ6JagJbPHweVWhmnpUta16sRotr3iZ73xz1BLIn9v2gb9LkP4gk00qcp+eGEHMFozam/Ve2NfBFYbnrdzqnSYxBL29//tSNC0q/jZrfPQIclq1NwmTvRdVw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7FB9E385800F Received: from localhost.localdomain (unknown [122.8.183.87]) by APP-05 (Coremail) with SMTP id zQCowADX3ipGP35nHlcFBg--.25663S4; Wed, 08 Jan 2025 17:03:17 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, jeffreyalaw@gmail.com, juzhe.zhong@rivai.ai, pan2.li@intel.com, monk.chiang@sifive.com, yihsiu.hsu@sifive.com, wuwei2016@iscas.ac.cn, jiawei@iscas.ac.cn, shihua@iscas.ac.cn, chenyixuan@iscas.ac.cn, yulong Subject: [PATCH V4 2/2] RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions. Date: Wed, 8 Jan 2025 17:02:55 +0800 Message-Id: <20250108090255.3755211-3-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250108090255.3755211-1-shiyulong@iscas.ac.cn> References: <20250108090255.3755211-1-shiyulong@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowADX3ipGP35nHlcFBg--.25663S4 X-Coremail-Antispam: 1UD129KBjvAXoWfGFy7Gr4UGw4rZFy8ZFWxCrg_yoW8XFy3to Z0ywn5JanxJwsa93sruw4UJF17twn3CryDGa9xu3yav3W8W3WFq34YkryFka18tr1Ikayr Zan3tr1UJa4fCFyxn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOh7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC2 0s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI 0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE 14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20x vaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8 JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbSksDUUUUU== X-Originating-IP: [122.8.183.87] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: yulong This commit adds testcases for Xsfvcp. Diff with V3: Change h file from riscv_vector.h to sifive_vector.h. Co-Authored by: Jiawei Chen Co-Authored by: Shihua Liao Co-Authored by: Yixuan Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xsfvector/sf_vc_f.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vc_i.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vc_v.c: New test. * gcc.target/riscv/rvv/xsfvector/sf_vc_x.c: New test. --- .../gcc.target/riscv/rvv/xsfvector/sf_vc_f.c | 88 +++++++++++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_i.c | 132 +++++++++++++++++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_v.c | 107 ++++++++++++++ .../gcc.target/riscv/rvv/xsfvector/sf_vc_x.c | 138 ++++++++++++++++++ 4 files changed, 465 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c new file mode 100644 index 00000000000..7667e56a4c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + +typedef _Float16 float16_t; +typedef float float32_t; +typedef double float64_t; + +/* +** test_sf_vc_v_fv_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fv_se_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl); +} + +/* +** test_sf_vc_fv_se_u16mf2: +** ... +** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+ +** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fvv_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fvv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl); +} + +/* +** test_sf_vc_fvv_se_u32m8: +** ... +** vsetivli\s+zero+,0+,e32+,m8,ta,ma+ +** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl); +} + + +/* +** test_sf_vc_fvw_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c new file mode 100644 index 00000000000..5528cc52ac7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + + +/* +** test_sf_vc_v_i_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) { + return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl); +} + +/* +** test_sf_vc_v_i_se_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) { + return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl); +} + +/* +** test_sf_vc_i_se_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_i_se_u16mf4(size_t vl) { + __riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl); +} + +/* +** test_sf_vc_v_iv_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_iv_u32m2(vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u32m2(1, vs2, 4, vl); +} + +/* +** test_sf_vc_v_iv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_iv_se_u32m2(vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u32m2(1, vs2, 4, vl); +} + +/* +** test_sf_vc_iv_se_u16m2: +** ... +** vsetivli\s+zero+,0+,e16+,m2,ta,ma+ +** sf\.vc\.iv\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_iv_se_u16m2(vuint16m2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16m2(1, 3, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivv_u8m8: +** ... +** vsetivli\s+zero+,0+,e8+,m8,ta,ma+ +** sf\.vc\.v\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint8m8_t test_sf_vc_v_ivv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8m8(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivv_se_u8m8: +** ... +** vsetivli\s+zero+,0+,e8+,m8,ta,ma+ +** sf\.vc\.v\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint8m8_t test_sf_vc_v_ivv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8m8(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_ivv_se_u64m1: +** ... +** vsetivli\s+zero+,0+,e64+,m1,ta,ma+ +** sf\.vc\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_ivv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u64m1(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivw_u8mf4: +** ... +** vsetivli\s+zero+,0+,e8+,mf4,ta,ma+ +** sf\.vc\.v\.ivw\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16mf2_t test_sf_vc_v_ivw_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8mf4(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivw_se_u8mf4: +** ... +** vsetivli\s+zero+,0+,e8+,mf4,ta,ma+ +** sf\.vc\.v\.ivw\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16mf2_t test_sf_vc_v_ivw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8mf4(1, vd, vs2, 4, vl); +} + +void test_sf_vc_ivw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u32m4(1, vd, vs2, 4, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c new file mode 100644 index 00000000000..e3022c14838 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c @@ -0,0 +1,107 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + + +/* +** test_sf_vc_v_vv_u8mf8: +** ... +** vsetivli\s+zero+,0+,e8+,mf8,ta,ma+ +** sf\.vc\.v\.vv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint8mf8_t test_sf_vc_v_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t rs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8mf8(1, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vv_se_u8mf8: +** ... +** vsetivli\s+zero+,0+,e8+,mf8,ta,ma+ +** sf\.vc\.v\.vv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint8mf8_t test_sf_vc_v_vv_se_u8mf8(vuint8mf8_t vs2, vuint8mf8_t rs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8mf8(1, vs2, rs1, vl); +} + +/* +** test_sf_vc_vv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.vv\t[0-9]+,[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vv_se_u16m1(vuint16m1_t vs2, vuint16m1_t rs1, size_t vl) { + __riscv_sf_vc_vv_se_u16m1(1, 3, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvv_u32mf2: +** ... +** vsetivli\s+zero+,0+,e32+,mf2,ta,ma+ +** sf\.vc\.v\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint32mf2_t test_sf_vc_v_vvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u32mf2(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvv_se_u32mf2: +** ... +** vsetivli\s+zero+,0+,e32+,mf2,ta,ma+ +** sf\.vc\.v\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint32mf2_t test_sf_vc_v_vvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u32mf2(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_vvv_se_u64m1: +** ... +** vsetivli\s+zero+,0+,e64+,m1,ta,ma+ +** sf\.vc\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t rs1, size_t vl) { + __riscv_sf_vc_vvv_se_u64m1(1, vd, vs2, rs1, vl); +} + + +/* +** test_sf_vc_v_vvw_u8m1: +** ... +** vsetivli\s+zero+,0+,e8+,m1,ta,ma+ +** sf\.vc\.v\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint16m2_t test_sf_vc_v_vvw_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8m1(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvw_se_u8m1: +** ... +** vsetivli\s+zero+,0+,e8+,m1,ta,ma+ +** sf\.vc\.v\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint16m2_t test_sf_vc_v_vvw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8m1(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_vvw_se_u16mf2: +** ... +** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+ +** sf\.vc\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, vuint16mf2_t rs1, size_t vl) { + __riscv_sf_vc_vvw_se_u16mf2(1, vd, vs2, rs1, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c new file mode 100644 index 00000000000..10c92c8c112 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c @@ -0,0 +1,138 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + +/* +** test_sf_vc_v_x_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.x\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m1_t test_sf_vc_v_x_u32m1(uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_x_u32m1(1, 2, xs1, vl); +} + +/* +** test_sf_vc_v_x_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.x\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m1_t test_sf_vc_v_x_se_u32m1(uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u32m1(1, 2, xs1, vl); +} + +/* +** test_sf_vc_x_se_u16m8: +** ... +** vsetivli\s+zero+,0+,e16+,m8,ta,ma+ +** sf\.vc\.x\t[0-9]+,[0-9]+,[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_x_se_u16m8(uint16_t xs1, size_t vl) { + __riscv_sf_vc_x_se_u16m8(1, 2, 3, xs1, vl); +} + +/* +** test_sf_vc_v_xv_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.xv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_xv_u32m2(vuint32m2_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xv_u32m2(1, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.xv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_xv_se_u32m2(vuint32m2_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u32m2(1, vs2, xs1, vl); +} + +/* +** test_sf_vc_xv_se_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.xv\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xv_se_u16m4(vuint16m4_t vs2, uint16_t xs1, size_t vl) { + __riscv_sf_vc_xv_se_u16m4(1, 3, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvv_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_xvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_xvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_xvv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t xs1, size_t vl) { + __riscv_sf_vc_xvv_se_u32m2(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvw_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint64m2_t test_sf_vc_v_xvw_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u32m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvw_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint64m2_t test_sf_vc_v_xvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u32m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_xvw_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + __riscv_sf_vc_xvw_se_u32m1(1, vd, vs2, xs1, vl); +} +