From patchwork Mon Dec 23 06:51:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yunzezhu@linux.alibaba.com X-Patchwork-Id: 103638 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 74367385842D for ; Mon, 23 Dec 2024 06:52:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 74367385842D Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.a=rsa-sha256 header.s=default header.b=TyQ9HBSU X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by sourceware.org (Postfix) with ESMTPS id A5E4D3858D1E for ; Mon, 23 Dec 2024 06:51:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A5E4D3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A5E4D3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.110 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1734936701; cv=none; b=fLs365ybGS3gDYx49Y9zR7V/e92M2jWUHX2awpAeOSc4ZyIDsgSg17A/rEE8ON/7/P7FDyDWsvplS1w8x+LYCBsSxeuWwJjgZ3KSjCk56c1iHjVj8aIAvXJjrdxInqXJAv5Azf/Q6+GmSI3cAHSQJ7grgcZysQOnx2djQ6FEu3s= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1734936701; c=relaxed/simple; bh=Zb36oDZf2rH544LS/AlKWiKNQ/9bcJV09lSYNP8eCIA=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=PlbFFnC8gytxulOaqhhrm8owP3lrh+AO3g36cs9IFRbMMD36yfGUgn5WybeqX1OAczyqGcUb50JgEKk1ijqLIGQ0kQHOLov49z9u59uhvIgokgQiNARNSjzUUOyGKVGetlRoNcSfJOJX/rSToKCPAwj6ALsbXkSp8HMV42MSh0k= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A5E4D3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1734936698; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=hRtrOTQc5AzqoagEXDfphhYSRcaI9sGFORo5N6xeltQ=; b=TyQ9HBSU1ymXkm2wHSNfNWK+ML47zCFvZQlaNnZ0GJRWE3yGKzDMw/pH3sKOdvJq28pFFMBrR8QQ2ZElMAH0c2856SI3fAXKI8Rcrw4sGmmm1KGDU9kRei5sAgbUQnjCuC3OCNqmzTiWM7avYWl6G1sPBmENq2J9nzOzgcJJthY= Received: from localhost(mailfrom:yunzezhu@linux.alibaba.com fp:SMTPD_---0WM0H9wC_1734936694 cluster:ay36) by smtp.aliyun-inc.com; Mon, 23 Dec 2024 14:51:34 +0800 From: yunzezhu@linux.alibaba.com To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, juzhe.zhong@rivai.ai, christoph.muellner@vrull.eu, Yunze Zhu Subject: [RFC PATCH v2] RISC-V:Fix th.vsetvli generates from vext_x_v with wrong operand Date: Mon, 23 Dec 2024 14:51:29 +0800 Message-Id: <20241223065129.34074-1-yunzezhu@linux.alibaba.com> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20241219025010.37997-1-yunzezhu@linux.alibaba.com> References: <20241219025010.37997-1-yunzezhu@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-29.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, USER_IN_DEF_DKIM_WL, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Yunze Zhu Fix a bug th.vsetvli generates from vext_x_v with an imm operand, which reports illegal operand. This patch fix this by replacing imm operand with reg operand in th.vsetvli. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc: gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/vext_x_v.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 2 +- .../riscv/rvv/xtheadvector/vext_x_v.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vext_x_v.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 720d52964c1c..e6ee074c19fb 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -1186,7 +1186,7 @@ public: set the value of avl to (const_int 0) so that VSETVL PASS will insert vsetvl correctly.*/ if (!get_avl ()) - avl = GEN_INT (0); + avl = TARGET_XTHEADVECTOR ? gen_rtx_REG (Pmode, 0) : GEN_INT (0); rtx sew = gen_int_mode (get_sew (), Pmode); rtx vlmul = gen_int_mode (get_vlmul (), Pmode); rtx ta = gen_int_mode (get_ta (), Pmode); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vext_x_v.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vext_x_v.c new file mode 100644 index 000000000000..be5847727cac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vext_x_v.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcxtheadvector -mabi=lp64d -O3 " } */ +#include + +int64_t f1 (void * in) +{ + vint64m1_t v = __riscv_th_vlb_v_i64m1 (in, 2); + vint32m1_t v2 = __riscv_th_vlb_v_i32m1 (in, 2); + int64_t i1 = __riscv_th_vext_x_v_i64m1_i64(v, 2); + int32_t i2 = __riscv_th_vext_x_v_i32m1_i32(v2, 2); + int64_t i = i1 + (int64_t)i2; + return i; +} + +/* { dg-final { scan-assembler-times "th.vsetvli zero,zero,e32,m1" 1 } } */ +/* { dg-final { scan-assembler-times "th.vsetvli zero,zero,e64,m1" 1 } } */ +/* { dg-final { scan-assembler-not "th.vsetvli zero,0" } } */