[1/3] arm, mve: Fix scan-assembler for test7 in dlstp-compile-asm-2.c
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Commit Message
After the changes to the vctp intrinsic codegen changed slightly, where we now
unfortunately seem to be generating unneeded moves and extends of the mask.
These are however not incorrect and we don't have a fix for the unneeded
codegen right now, so changing the testcase to accept them so we can catch
other changes if they occur.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/dlstp-compile-asm-2.c (test7): Add an optional
vmsr to the check-function-bodies.
---
gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c | 1 +
1 file changed, 1 insertion(+)
Comments
On 11/29/24 11:30, Andre Vieira wrote:
>
> After the changes to the vctp intrinsic codegen changed slightly, where we now
> unfortunately seem to be generating unneeded moves and extends of the mask.
> These are however not incorrect and we don't have a fix for the unneeded
> codegen right now, so changing the testcase to accept them so we can catch
> other changes if they occur.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arm/mve/dlstp-compile-asm-2.c (test7): Add an optional
> vmsr to the check-function-bodies.
Indeed I've been looking at avoiding these extra moves but did not find
a good solution yet.
In the mean time I agree it's reasonable to update the testcase for gcc-15.
Thanks,
Christophe
> ---
> gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c | 1 +
> 1 file changed, 1 insertion(+)
>
@@ -216,6 +216,7 @@ void test7 (int32_t *a, int32_t *b, int32_t *c, int n, int g)
**...
** dlstp.32 lr, r3
** vldrw.32 q[0-9]+, \[r0\], #16
+** (?:vmsr p0, .*)
** vpst
** vldrwt.32 q[0-9]+, \[r1\], #16
** vadd.i32 (q[0-9]+), q[0-9]+, q[0-9]+