Message ID | 20241129035404.3363162-2-tejas.belagod@arm.com |
---|---|
State | Committed |
Commit | 65df27bb0ca5ccecf335a64fdfe954119c9095cd |
Headers |
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Fri, 29 Nov 2024 03:54:10 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EXJ01.Arm.com (10.240.25.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 29 Nov 2024 03:54:09 +0000 Received: from a078660.blr.arm.com (10.162.46.14) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 29 Nov 2024 03:54:08 +0000 From: Tejas Belagod <tejas.belagod@arm.com> To: <gcc-patches@gcc.gnu.org> CC: Tejas Belagod <tejas.belagod@arm.com>, <richard.sandiford@arm.com>, <rguenther@suse.de>, <josmyers@redhat.com>, <jason@redhat.com>, <polacek@redhat.com> Subject: [PATCH v3 1/8] aarch64: Fix ACLE macro __ARM_FEATURE_SVE_VECTOR_OPERATORS Date: Fri, 29 Nov 2024 09:23:57 +0530 Message-ID: <20241129035404.3363162-2-tejas.belagod@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241129035404.3363162-1-tejas.belagod@arm.com> References: <20241129035404.3363162-1-tejas.belagod@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DB1PEPF00050A01:EE_|PA4PR08MB6141:EE_|AMS1EPF0000003F:EE_|PA6PR08MB10566:EE_ X-MS-Office365-Filtering-Correlation-Id: faa866c2-f090-4dda-a1cc-08dd102981f4 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Series |
aarch64: Enable C/C++ operations on SVE ACLE types.
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Commit Message
Tejas Belagod
Nov. 29, 2024, 3:53 a.m. UTC
This patch enables ACLE macro __ARM_FEATURE_SVE_VECTOR_OPERATORS to indicate that C/C++ language operations are available natively on SVE ACLE types. gcc/ChangeLog: * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Define __ARM_FEATURE_SVE_VECTOR_OPERATORS. --- gcc/config/aarch64/aarch64-c.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc index 689c763cd45..3cc2c97c6d8 100644 --- a/gcc/config/aarch64/aarch64-c.cc +++ b/gcc/config/aarch64/aarch64-c.cc @@ -193,15 +193,19 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_SIMD_RDMA, "__ARM_FEATURE_QRDMX", pfile); aarch64_def_or_undef (TARGET_SVE, "__ARM_FEATURE_SVE", pfile); cpp_undef (pfile, "__ARM_FEATURE_SVE_BITS"); + cpp_undef (pfile, "__ARM_FEATURE_SVE_VECTOR_OPERATORS"); if (TARGET_SVE) { int bits; + int ops = 1; if (!BITS_PER_SVE_VECTOR.is_constant (&bits)) - bits = 0; + { + bits = 0; + ops = 2; + } builtin_define_with_int_value ("__ARM_FEATURE_SVE_BITS", bits); + builtin_define_with_int_value ("__ARM_FEATURE_SVE_VECTOR_OPERATORS", ops); } - aarch64_def_or_undef (TARGET_SVE, "__ARM_FEATURE_SVE_VECTOR_OPERATORS", - pfile); aarch64_def_or_undef (TARGET_SVE_I8MM, "__ARM_FEATURE_SVE_MATMUL_INT8", pfile); aarch64_def_or_undef (TARGET_SVE_F32MM,