From patchwork Wed Nov 27 09:46:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinyang He X-Patchwork-Id: 101956 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0D44A3857B84 for ; Wed, 27 Nov 2024 09:47:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0D44A3857B84 X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 351813858C35 for ; Wed, 27 Nov 2024 09:46:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 351813858C35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 351813858C35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1732700801; cv=none; b=ZyQNe5YSed1/LRS3pnoSjQII/ZNga7i3pZ99AA4RHRMQPlR4Ufc9C3OeVRE/eMn+wMKdBTbarT2Nx/0sxjTuI3VDDJ4OClK74TXs6pjDCee+AlgBVW4lb+6tquon1nsPvy0NF3xoCmIcv4JRLdwoFS18T4CcGG+sNuH9iDcmZ8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1732700801; c=relaxed/simple; bh=lwjfqvcUkvrYbrpAbqPw3PflcO5x1TLrUGXGuOBvDtU=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=qtFmweGAXFpR9Ns/dtRAgNwNvJzkXzqpOAPTR9gfjkzxwOpXK4/hWuExCoC8YNosGJXrltiGsV4PuemZrkWcCmPhfjnTz9JG8ky62LgW020xsTF7rnIdO4K7+xlOCBaMLVcRNTy8/sjhOJK+yXr1aOJ5d9UmifgUIE7XFm6YzKI= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 351813858C35 Received: from loongson.cn (unknown [111.9.175.10]) by gateway (Coremail) with SMTP id _____8Dxfa976kZn48BJAA--.54591S3; Wed, 27 Nov 2024 17:46:35 +0800 (CST) Received: from localhost.localdomain (unknown [111.9.175.10]) by front1 (Coremail) with SMTP id qMiowMBx_uBy6kZnl7hpAA--.22153S2; Wed, 27 Nov 2024 17:46:28 +0800 (CST) From: Jinyang He To: Lulu Cheng , Xi Ruoyao Cc: gcc-patches@gcc.gnu.org, Chenghua Xu , Jinyang He Subject: [PATCH v2] LoongArch: Mask shift offset when emit {xv, v}{srl, sll, sra} with sameimm vector Date: Wed, 27 Nov 2024 17:46:26 +0800 Message-Id: <20241127094626.18201-1-hejinyang@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: qMiowMBx_uBy6kZnl7hpAA--.22153S2 X-CM-SenderInfo: pkhmx0p1dqwqxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj9fXoW3tw18WrWxWw4DWr1UKrW7GFX_yoW8XFWxWo WFyF4qyF18Gr43C398Cwn3XFWvqa1Ykr4kAasxZF45CF4xJrWqyr9xW3WYv34Sy3Z8ZayU JF97Awn7Xasxtw48l-sFpf9Il3svdjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8wcxFpf 9Il3svdxBIdaVrn0xqx4xG64xvF2IEw4CE5I8CrVC2j2Jv73VFW2AGmfu7bjvjm3AaLaJ3 UjIYCTnIWjp_UUUY17kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI 8IcIk0rVWrJVCq3wAFIxvE14AKwVWUGVWUXwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xG Y2AK021l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14 v26r1j6r4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAF wI0_Gr1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI 0UMc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280 aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxU25EfUUUUU X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow in when emit {w,h,b}. Since the number of bits shifted is the remainder of the register value, it is actually unnecessary to constrain the range. Simply mask the shift number with the unit-bit-width, without any constraint on the shift range. gcc/ChangeLog: * config/loongarch/constraints.md (Uuv6, Uuvx): Remove Uuv6, add Uuvx as replicated vector const with unsigned range [0,umax]. * config/loongarch/lasx.md (xvsrl, xvsra, xvsll): Mask shift offset by its unit bits. * config/loongarch/lsx.md (vsrl, vsra, vsll): Likewise. * config/loongarch/loongarch-protos.h (loongarch_const_vector_same_int_p): Set default for low and high. * config/loongarch/predicates.md: Replace reg_or_vector_same_uimm6 _operand to reg_or_vector_same_uimm_operand. gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c: New test. * gcc.target/loongarch/vector/lsx/lsx-shift-sameimm-vec.c: New test. --- v2: Fix indent in lsx.md and lasx.md. Use "dg-do assemble" in test which suggested by Ruoyao. gcc/config/loongarch/constraints.md | 14 ++--- gcc/config/loongarch/lasx.md | 60 +++++++++++++++---- gcc/config/loongarch/loongarch-protos.h | 5 +- gcc/config/loongarch/lsx.md | 60 +++++++++++++++---- gcc/config/loongarch/predicates.md | 8 +-- .../vector/lasx/lasx-shift-sameimm-vec.c | 48 +++++++++++++++ .../vector/lsx/lsx-shift-sameimm-vec.c | 48 +++++++++++++++ 7 files changed, 206 insertions(+), 37 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-shift-sameimm-vec.c diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md index 18da8b31f49..66ef1073fad 100644 --- a/gcc/config/loongarch/constraints.md +++ b/gcc/config/loongarch/constraints.md @@ -334,19 +334,19 @@ (and (match_code "const_vector") (match_test "loongarch_const_vector_same_int_p (op, mode, -16, 15)"))) -(define_constraint "Uuv6" - "@internal - A replicated vector const in which the replicated value is in the range - [0,63]." - (and (match_code "const_vector") - (match_test "loongarch_const_vector_same_int_p (op, mode, 0, 63)"))) - (define_constraint "Urv8" "@internal A replicated vector const with replicated byte values as well as elements" (and (match_code "const_vector") (match_test "loongarch_const_vector_same_bytes_p (op, mode)"))) +(define_constraint "Uuvx" + "@internal + A replicated vector const in which the replicated value is in the unsigned + range [0,umax]." + (and (match_code "const_vector") + (match_test "loongarch_const_vector_same_int_p (op, mode)"))) + (define_memory_constraint "ZC" "A memory operand whose address is formed by a base register and offset that is suitable for use in instructions with the same addressing mode diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 457ed163f31..90778dd8ff9 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -1013,11 +1013,23 @@ [(set (match_operand:ILASX 0 "register_operand" "=f,f") (lshiftrt:ILASX (match_operand:ILASX 1 "register_operand" "f,f") - (match_operand:ILASX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] + (match_operand:ILASX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))] "ISA_HAS_LASX" - "@ - xvsrl.\t%u0,%u1,%u2 - xvsrli.\t%u0,%u1,%E2" +{ + switch (which_alternative) + { + case 0: + return "xvsrl.\t%u0,%u1,%u2"; + case 1: + { + unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0)); + operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (mode) - 1)); + return "xvsrli.\t%u0,%u1,%d2"; + } + default: + gcc_unreachable (); + } +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) @@ -1026,11 +1038,23 @@ [(set (match_operand:ILASX 0 "register_operand" "=f,f") (ashiftrt:ILASX (match_operand:ILASX 1 "register_operand" "f,f") - (match_operand:ILASX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] + (match_operand:ILASX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))] "ISA_HAS_LASX" - "@ - xvsra.\t%u0,%u1,%u2 - xvsrai.\t%u0,%u1,%E2" +{ + switch (which_alternative) + { + case 0: + return "xvsra.\t%u0,%u1,%u2"; + case 1: + { + unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0)); + operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (mode) - 1)); + return "xvsrai.\t%u0,%u1,%d2"; + } + default: + gcc_unreachable (); + } +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) @@ -1039,11 +1063,23 @@ [(set (match_operand:ILASX 0 "register_operand" "=f,f") (ashift:ILASX (match_operand:ILASX 1 "register_operand" "f,f") - (match_operand:ILASX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] + (match_operand:ILASX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))] "ISA_HAS_LASX" - "@ - xvsll.\t%u0,%u1,%u2 - xvslli.\t%u0,%u1,%E2" +{ + switch (which_alternative) + { + case 0: + return "xvsll.\t%u0,%u1,%u2"; + case 1: + { + unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0)); + operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (mode) - 1)); + return "xvslli.\t%u0,%u1,%d2"; + } + default: + gcc_unreachable (); + } +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h index bc1b94b41d3..be37f284f39 100644 --- a/gcc/config/loongarch/loongarch-protos.h +++ b/gcc/config/loongarch/loongarch-protos.h @@ -113,8 +113,9 @@ extern rtx loongarch_return_addr (int, rtx); extern bool loongarch_const_vector_same_val_p (rtx, machine_mode); extern bool loongarch_const_vector_same_bytes_p (rtx, machine_mode); -extern bool loongarch_const_vector_same_int_p (rtx, machine_mode, HOST_WIDE_INT, - HOST_WIDE_INT); +extern bool loongarch_const_vector_same_int_p (rtx, machine_mode, + HOST_WIDE_INT low = HOST_WIDE_INT_MIN, + HOST_WIDE_INT high = HOST_WIDE_INT_MAX); extern bool loongarch_const_vector_shuffle_set_p (rtx, machine_mode); extern bool loongarch_const_vector_bitimm_set_p (rtx, machine_mode); extern bool loongarch_const_vector_bitimm_clr_p (rtx, machine_mode); diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index a9004290371..2466d8c87be 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -879,11 +879,23 @@ [(set (match_operand:ILSX 0 "register_operand" "=f,f") (lshiftrt:ILSX (match_operand:ILSX 1 "register_operand" "f,f") - (match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] + (match_operand:ILSX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))] "ISA_HAS_LSX" - "@ - vsrl.\t%w0,%w1,%w2 - vsrli.\t%w0,%w1,%E2" +{ + switch (which_alternative) + { + case 0: + return "vsrl.\t%w0,%w1,%w2"; + case 1: + { + unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0)); + operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (mode) - 1)); + return "vsrli.\t%w0,%w1,%d2"; + } + default: + gcc_unreachable (); + } +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) @@ -891,11 +903,23 @@ [(set (match_operand:ILSX 0 "register_operand" "=f,f") (ashiftrt:ILSX (match_operand:ILSX 1 "register_operand" "f,f") - (match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] + (match_operand:ILSX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))] "ISA_HAS_LSX" - "@ - vsra.\t%w0,%w1,%w2 - vsrai.\t%w0,%w1,%E2" +{ + switch (which_alternative) + { + case 0: + return "vsra.\t%w0,%w1,%w2"; + case 1: + { + unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0)); + operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (mode) - 1)); + return "vsrai.\t%w0,%w1,%d2"; + } + default: + gcc_unreachable (); + } +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) @@ -903,11 +927,23 @@ [(set (match_operand:ILSX 0 "register_operand" "=f,f") (ashift:ILSX (match_operand:ILSX 1 "register_operand" "f,f") - (match_operand:ILSX 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] + (match_operand:ILSX 2 "reg_or_vector_same_uimm_operand" "f,Uuvx")))] "ISA_HAS_LSX" - "@ - vsll.\t%w0,%w1,%w2 - vslli.\t%w0,%w1,%E2" +{ + switch (which_alternative) + { + case 0: + return "vsll.\t%w0,%w1,%w2"; + case 1: + { + unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (operands[2], 0)); + operands[2] = GEN_INT (val & (GET_MODE_UNIT_BITSIZE (mode) - 1)); + return "vslli.\t%w0,%w1,%d2"; + } + default: + gcc_unreachable (); + } +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md index 95c2544cc2f..e744e4e61ea 100644 --- a/gcc/config/loongarch/predicates.md +++ b/gcc/config/loongarch/predicates.md @@ -635,10 +635,10 @@ return loongarch_const_vector_same_int_p (op, mode, -31, 31); }) -(define_predicate "const_vector_same_uimm6_operand" +(define_predicate "const_vector_same_uimm_operand" (match_code "const_vector") { - return loongarch_const_vector_same_int_p (op, mode, 0, 63); + return loongarch_const_vector_same_int_p (op, mode); }) (define_predicate "par_const_vector_shf_set_operand" @@ -663,6 +663,6 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "const_vector_same_ximm5_operand"))) -(define_predicate "reg_or_vector_same_uimm6_operand" +(define_predicate "reg_or_vector_same_uimm_operand" (ior (match_operand 0 "register_operand") - (match_operand 0 "const_vector_same_uimm6_operand"))) + (match_operand 0 "const_vector_same_uimm_operand"))) diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c new file mode 100644 index 00000000000..fb79631c81a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c @@ -0,0 +1,48 @@ +/* Test shift bits overflow in vector */ +/* { dg-do assemble } */ +/* { dg-options "-mlasx -O2" } */ + +typedef signed char v32i8 __attribute__ ((vector_size (32), aligned (32))); +typedef short v16i16 __attribute__ ((vector_size (32), aligned (32))); +typedef int v8i32 __attribute__ ((vector_size (32), aligned (32))); +typedef long long v4i64 __attribute__ ((vector_size (32), aligned (32))); + +#define TWICE(_) _, _ +#define V32I8_RVAL(_) (v32i8) {TWICE(TWICE(TWICE(TWICE(TWICE(_)))))} +#define V16I16_RVAL(_) (v16i16) {TWICE(TWICE(TWICE(TWICE(_))))} +#define V8I32_RVAL(_) (v8i32) {TWICE(TWICE(TWICE(_)))} +#define V4I64_RVAL(_) (v4i64) {TWICE(TWICE(_))} + +#define TEST_FUNC(typ, key, inst, rept, val) \ +typ \ +_##key##inst (typ _) \ +{ \ + return __builtin_lasx_##inst(_, rept(val)); \ +} + +TEST_FUNC(v32i8, pos, xvsll_b, V32I8_RVAL, 65) +TEST_FUNC(v32i8, neg, xvsll_b, V32I8_RVAL, -65) +TEST_FUNC(v16i16, pos, xvsll_h, V16I16_RVAL, 65) +TEST_FUNC(v16i16, neg, xvsll_h, V16I16_RVAL, -65) +TEST_FUNC(v8i32, pos, xvsll_w, V8I32_RVAL, 65) +TEST_FUNC(v8i32, neg, xvsll_w, V8I32_RVAL, -65) +TEST_FUNC(v4i64, pos, xvsll_d, V4I64_RVAL, 65) +TEST_FUNC(v4i64, neg, xvsll_d, V4I64_RVAL, -65) + +TEST_FUNC(v32i8, pos, xvsrl_b, V32I8_RVAL, 65) +TEST_FUNC(v32i8, neg, xvsrl_b, V32I8_RVAL, -65) +TEST_FUNC(v16i16, pos, xvsrl_h, V16I16_RVAL, 65) +TEST_FUNC(v16i16, neg, xvsrl_h, V16I16_RVAL, -65) +TEST_FUNC(v8i32, pos, xvsrl_w, V8I32_RVAL, 65) +TEST_FUNC(v8i32, neg, xvsrl_w, V8I32_RVAL, -65) +TEST_FUNC(v4i64, pos, xvsrl_d, V4I64_RVAL, 65) +TEST_FUNC(v4i64, neg, xvsrl_d, V4I64_RVAL, -65) + +TEST_FUNC(v32i8, pos, xvsra_b, V32I8_RVAL, 65) +TEST_FUNC(v32i8, neg, xvsra_b, V32I8_RVAL, -65) +TEST_FUNC(v16i16, pos, xvsra_h, V16I16_RVAL, 65) +TEST_FUNC(v16i16, neg, xvsra_h, V16I16_RVAL, -65) +TEST_FUNC(v8i32, pos, xvsra_w, V8I32_RVAL, 65) +TEST_FUNC(v8i32, neg, xvsra_w, V8I32_RVAL, -65) +TEST_FUNC(v4i64, pos, xvsra_d, V4I64_RVAL, 65) +TEST_FUNC(v4i64, neg, xvsra_d, V4I64_RVAL, -65) diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-shift-sameimm-vec.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-shift-sameimm-vec.c new file mode 100644 index 00000000000..ea09feb0ea0 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-shift-sameimm-vec.c @@ -0,0 +1,48 @@ +/* Test shift bits overflow in vector */ +/* { dg-do assemble } */ +/* { dg-options "-mlsx -O2" } */ + +typedef signed char v16i8 __attribute__ ((vector_size (16), aligned (16))); +typedef short v8i16 __attribute__ ((vector_size (16), aligned (16))); +typedef int v4i32 __attribute__ ((vector_size (16), aligned (16))); +typedef long long v2i64 __attribute__ ((vector_size (16), aligned (16))); + +#define TWICE(_) _, _ +#define V16I8_RVAL(_) (v16i8) {TWICE(TWICE(TWICE(TWICE(_))))} +#define V8I16_RVAL(_) (v8i16) {TWICE(TWICE(TWICE(_)))} +#define V4I32_RVAL(_) (v4i32) {TWICE(TWICE(_))} +#define V2I64_RVAL(_) (v2i64) {TWICE(_)} + +#define TEST_FUNC(typ, key, inst, rept, val) \ +typ \ +_##key##inst (typ _) \ +{ \ + return __builtin_lsx_##inst(_, rept(val)); \ +} + +TEST_FUNC(v16i8, pos, vsll_b, V16I8_RVAL, 65) +TEST_FUNC(v16i8, neg, vsll_b, V16I8_RVAL, -65) +TEST_FUNC(v8i16, pos, vsll_h, V8I16_RVAL, 65) +TEST_FUNC(v8i16, neg, vsll_h, V8I16_RVAL, -65) +TEST_FUNC(v4i32, pos, vsll_w, V4I32_RVAL, 65) +TEST_FUNC(v4i32, neg, vsll_w, V4I32_RVAL, -65) +TEST_FUNC(v2i64, pos, vsll_d, V2I64_RVAL, 65) +TEST_FUNC(v2i64, neg, vsll_d, V2I64_RVAL, -65) + +TEST_FUNC(v16i8, pos, vsrl_b, V16I8_RVAL, 65) +TEST_FUNC(v16i8, neg, vsrl_b, V16I8_RVAL, -65) +TEST_FUNC(v8i16, pos, vsrl_h, V8I16_RVAL, 65) +TEST_FUNC(v8i16, neg, vsrl_h, V8I16_RVAL, -65) +TEST_FUNC(v4i32, pos, vsrl_w, V4I32_RVAL, 65) +TEST_FUNC(v4i32, neg, vsrl_w, V4I32_RVAL, -65) +TEST_FUNC(v2i64, pos, vsrl_d, V2I64_RVAL, 65) +TEST_FUNC(v2i64, neg, vsrl_d, V2I64_RVAL, -65) + +TEST_FUNC(v16i8, pos, vsra_b, V16I8_RVAL, 65) +TEST_FUNC(v16i8, neg, vsra_b, V16I8_RVAL, -65) +TEST_FUNC(v8i16, pos, vsra_h, V8I16_RVAL, 65) +TEST_FUNC(v8i16, neg, vsra_h, V8I16_RVAL, -65) +TEST_FUNC(v4i32, pos, vsra_w, V4I32_RVAL, 65) +TEST_FUNC(v4i32, neg, vsra_w, V4I32_RVAL, -65) +TEST_FUNC(v2i64, pos, vsra_d, V2I64_RVAL, 65) +TEST_FUNC(v2i64, neg, vsra_d, V2I64_RVAL, -65)