From patchwork Wed Oct 30 18:48:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 99844 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E018F3857C6C for ; Wed, 30 Oct 2024 18:52:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 32A3D3858D33 for ; Wed, 30 Oct 2024 18:49:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 32A3D3858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 32A3D3858D33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730314170; cv=none; b=fzBF05pFhfOt17Bby+B6pTor5P08VVpqgMSi0YejSwP8Uye6NdI+oSw0fnIX+lcuZ5bS2mEd0Gct3NMorzD3p3vDoFSyCbWbI2JS1MAZSs+FV830kO2x+b76zm4JOkwUjWQZBmDgIkiRekMxfMpoabIw2uirAagyrbAySfFrdtI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1730314170; c=relaxed/simple; bh=7vT9phiLGi6MxkOYdb51HeHROiIzKjergJQKdvvzPD0=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=gh1ofeS1uZL6TD3zpQLnPKtTBuoIN0cZkXs4J+B5S6tP/0Am+WHSPuch9Q6ivF+vyx5bPiLLmoToqsKI0Jeiix8ke0XAlQ3hgXlrqcxLT0MI0k8uk0Gbm16y+AG21iBkIHbjS2TpsxSJqO2n7O5AmA+3f3vwgzGQlEM8to5E498= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA8361A25; Wed, 30 Oct 2024 11:49:52 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5279F3F528; Wed, 30 Oct 2024 11:49:22 -0700 (PDT) From: Richard Sandiford To: richard.earnshaw@arm.com, ktkachov@nvidia.com, gcc-patches@gcc.gnu.org Cc: Richard Sandiford Subject: [PATCH 3/3] aarch64: Require SVE2 and/or SME2 for SVE FAMINMAX intrinsics Date: Wed, 30 Oct 2024 18:48:30 +0000 Message-Id: <20241030184830.3634301-4-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241030184830.3634301-1-richard.sandiford@arm.com> References: <20241030184830.3634301-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-18.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org After the previous patch, we can now accurately model the ISA requirements for the SVE FAMINMAX intrinsics. They can be used in non-streaming mode if TARGET_SVE2 and in streaming mode if TARGET_SME2 (with both cases also requiring TARGET_FAMINMAX). They can be used in streaming-compatible mode if TARGET_SVE2 && TARGET_SME2. Also, Kyrill pointed out in the original review of the FAMINMAX support that it would be more consistent to define the rtl patterns in aarch64-sve2.md rather than aarch64-sve.md, so the pushed patch did that. This patch moves the definitions of the intrinsics to the sve2 files too, for consistency. gcc/ * config/aarch64/aarch64-sve-builtins-base.cc (svmax, svamin): Move definitions to... * config/aarch64/aarch64-sve-builtins-sve2.cc: ...here. * config/aarch64/aarch64-sve-builtins-base.def (svmax, svamin): Move definitions to... * config/aarch64/aarch64-sve-builtins-sve2.def: ...here. Require SME2 in streaming mode. gcc/testsuite/ * gcc.target/aarch64/sve/acle/general/amin_1.c: New test. * gcc.target/aarch64/sve2/acle/asm/amax_f16.c: Enabled sve2 and (for streaming mode) sme2. * gcc.target/aarch64/sve2/acle/asm/amax_f32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/amax_f64.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/amin_f16.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/amin_f32.c: Likewise. * gcc.target/aarch64/sve2/acle/asm/amin_f64.c: Likewise. --- gcc/config/aarch64/aarch64-sve-builtins-base.cc | 4 ---- gcc/config/aarch64/aarch64-sve-builtins-base.def | 5 ----- gcc/config/aarch64/aarch64-sve-builtins-sve2.cc | 4 ++++ gcc/config/aarch64/aarch64-sve-builtins-sve2.def | 7 +++++++ .../gcc.target/aarch64/sve/acle/general/amin_1.c | 9 +++++++++ .../gcc.target/aarch64/sve2/acle/asm/amax_f16.c | 5 ++++- .../gcc.target/aarch64/sve2/acle/asm/amax_f32.c | 5 ++++- .../gcc.target/aarch64/sve2/acle/asm/amax_f64.c | 5 ++++- .../gcc.target/aarch64/sve2/acle/asm/amin_f16.c | 5 ++++- .../gcc.target/aarch64/sve2/acle/asm/amin_f32.c | 5 ++++- .../gcc.target/aarch64/sve2/acle/asm/amin_f64.c | 5 ++++- 11 files changed, 44 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/amin_1.c diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index fe16d93adcd..1c9f515a52c 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -3184,10 +3184,6 @@ FUNCTION (svadrb, svadr_bhwd_impl, (0)) FUNCTION (svadrd, svadr_bhwd_impl, (3)) FUNCTION (svadrh, svadr_bhwd_impl, (1)) FUNCTION (svadrw, svadr_bhwd_impl, (2)) -FUNCTION (svamax, cond_or_uncond_unspec_function, - (UNSPEC_COND_FAMAX, UNSPEC_FAMAX)) -FUNCTION (svamin, cond_or_uncond_unspec_function, - (UNSPEC_COND_FAMIN, UNSPEC_FAMIN)) FUNCTION (svand, rtx_code_function, (AND, AND)) FUNCTION (svandv, reduction, (UNSPEC_ANDV)) FUNCTION (svasr, rtx_code_function, (ASHIFTRT, ASHIFTRT)) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.def b/gcc/config/aarch64/aarch64-sve-builtins-base.def index edfe2574507..da2a0e41aa5 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.def @@ -368,8 +368,3 @@ DEF_SVE_FUNCTION (svuzp2q, binary, all_data, none) DEF_SVE_FUNCTION (svzip1q, binary, all_data, none) DEF_SVE_FUNCTION (svzip2q, binary, all_data, none) #undef REQUIRED_EXTENSIONS - -#define REQUIRED_EXTENSIONS ssve (AARCH64_FL_FAMINMAX) -DEF_SVE_FUNCTION (svamax, binary_opt_single_n, all_float, mxz) -DEF_SVE_FUNCTION (svamin, binary_opt_single_n, all_float, mxz) -#undef REQUIRED_EXTENSIONS diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc index d29c2209fdf..64f86035c30 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.cc @@ -591,6 +591,10 @@ FUNCTION (svaesd, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesd)) FUNCTION (svaese, fixed_insn_function, (CODE_FOR_aarch64_sve2_aese)) FUNCTION (svaesimc, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesimc)) FUNCTION (svaesmc, fixed_insn_function, (CODE_FOR_aarch64_sve2_aesmc)) +FUNCTION (svamax, cond_or_uncond_unspec_function, + (UNSPEC_COND_FAMAX, UNSPEC_FAMAX)) +FUNCTION (svamin, cond_or_uncond_unspec_function, + (UNSPEC_COND_FAMIN, UNSPEC_FAMIN)) FUNCTION (svbcax, CODE_FOR_MODE0 (aarch64_sve2_bcax),) FUNCTION (svbdep, unspec_based_function, (UNSPEC_BDEP, UNSPEC_BDEP, -1)) FUNCTION (svbext, unspec_based_function, (UNSPEC_BEXT, UNSPEC_BEXT, -1)) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def index 345a7621b6f..e4021559f36 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-sve2.def +++ b/gcc/config/aarch64/aarch64-sve-builtins-sve2.def @@ -283,3 +283,10 @@ DEF_SVE_FUNCTION (svwhilelt, compare_scalar_count, while_x_c, none) DEF_SVE_FUNCTION_GS (svzip, unaryxn, all_data, x24, none) DEF_SVE_FUNCTION_GS (svzipq, unaryxn, all_data, x24, none) #undef REQUIRED_EXTENSIONS + +#define REQUIRED_EXTENSIONS \ + sve_and_sme (AARCH64_FL_SVE2 | AARCH64_FL_FAMINMAX, \ + AARCH64_FL_SME2 | AARCH64_FL_FAMINMAX) +DEF_SVE_FUNCTION (svamax, binary_opt_single_n, all_float, mxz) +DEF_SVE_FUNCTION (svamin, binary_opt_single_n, all_float, mxz) +#undef REQUIRED_EXTENSIONS diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/amin_1.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/amin_1.c new file mode 100644 index 00000000000..e2c28cfaf62 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/amin_1.c @@ -0,0 +1,9 @@ +#include + +#pragma GCC target "+nosme2+sve2+faminmax+sme" + +svfloat32_t +foo (svfloat32_t x, svfloat32_t y) __arm_streaming +{ + return svamin_x (svptrue_b8 (), x, y); /* { dg-error {ACLE function '[^']*' requires ISA extension 'sme2'} } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c index 3d99e4bd92d..43c1e4d9c51 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f16.c @@ -3,7 +3,10 @@ #include "test_sve_acle.h" -#pragma GCC target "+sve+faminmax" +#pragma GCC target "+sve2+faminmax" +#if STREAMING_COMPATIBLE +#pragma GCC target "+sme2" +#endif /* ** amax_f16_m_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f32.c index 686996625fb..56e6b7333a0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f32.c @@ -3,7 +3,10 @@ #include "test_sve_acle.h" -#pragma GCC target "+sve+faminmax" +#pragma GCC target "+sve2+faminmax" +#if STREAMING_COMPATIBLE +#pragma GCC target "+sme2" +#endif /* ** amax_f32_m_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f64.c index e0f0ac32e54..458c7051702 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amax_f64.c @@ -3,7 +3,10 @@ #include "test_sve_acle.h" -#pragma GCC target "+sve+faminmax" +#pragma GCC target "+sve2+faminmax" +#if STREAMING_COMPATIBLE +#pragma GCC target "+sme2" +#endif /* ** amax_f64_m_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f16.c index f93aed6cba5..4c36c425493 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f16.c @@ -3,7 +3,10 @@ #include "test_sve_acle.h" -#pragma GCC target "+sve+faminmax" +#pragma GCC target "+sve2+faminmax" +#if STREAMING_COMPATIBLE +#pragma GCC target "+sme2" +#endif /* ** amin_f16_m_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f32.c index cc1a343160e..56943fc0657 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f32.c @@ -3,7 +3,10 @@ #include "test_sve_acle.h" -#pragma GCC target "+sve+faminmax" +#pragma GCC target "+sve2+faminmax" +#if STREAMING_COMPATIBLE +#pragma GCC target "+sme2" +#endif /* ** amin_f32_m_tied1: diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f64.c index b5133f12950..a93f7d687f5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/amin_f64.c @@ -3,7 +3,10 @@ #include "test_sve_acle.h" -#pragma GCC target "+sve+faminmax" +#pragma GCC target "+sve2+faminmax" +#if STREAMING_COMPATIBLE +#pragma GCC target "+sme2" +#endif /* ** amin_f64_m_tied1: