diff mbox series

[v4,2/2] RISC-V: Add testcases for unsigned .SAT_SUB form 2 with IMM = 1.

Message ID 20241025012212.33101-2-xuli1@eswincomputing.com
State Committed
Commit 179a682d047500604c6612afb425acf481e1a6b2
Delegated to: Jeff Law
Headers
Series [v4,1/2] Match: Simplify (x != 0 ? x + ~0 : 0) to (x - x != 0). |

Checks

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Commit Message

xuli1@eswincomputing.com Oct. 25, 2024, 1:22 a.m. UTC 
  From: xuli <xuli1@eswincomputing.com>

form2:
T __attribute__((noinline))             \
sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
{                                       \
  return x >= (T)IMM ? x - (T)IMM : 0;  \
}

Passed the rv64gcv regression test.

Signed-off-by: Li Xu <xuli1@eswincomputing.com>
gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_u_sub_imm-run-5.c: add run case for imm=1.
	* gcc.target/riscv/sat_u_sub_imm-run-6.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-run-7.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-run-8.c: Ditto.
	* gcc.target/riscv/sat_u_sub_imm-5_3.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-6_3.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-7_3.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-8_1.c: New test.
---
 .../gcc.target/riscv/sat_u_sub_imm-5_3.c      | 18 ++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-6_3.c      | 19 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-7_3.c      | 17 +++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-8_1.c      | 17 +++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-5.c    |  1 +
 .../gcc.target/riscv/sat_u_sub_imm-run-6.c    |  1 +
 .../gcc.target/riscv/sat_u_sub_imm-run-7.c    |  1 +
 .../gcc.target/riscv/sat_u_sub_imm-run-8.c    |  1 +
 8 files changed, 75 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c

Comments

Jeff Law Oct. 27, 2024, 7:44 p.m. UTC | #1 
On 10/24/24 7:22 PM, Li Xu wrote:
> From: xuli <xuli1@eswincomputing.com>
> 
> form2:
> T __attribute__((noinline))             \
> sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
> {                                       \
>    return x >= (T)IMM ? x - (T)IMM : 0;  \
> }
> 
> Passed the rv64gcv regression test.
> 
> Signed-off-by: Li Xu <xuli1@eswincomputing.com>
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/sat_u_sub_imm-run-5.c: add run case for imm=1.
> 	* gcc.target/riscv/sat_u_sub_imm-run-6.c: Ditto.
> 	* gcc.target/riscv/sat_u_sub_imm-run-7.c: Ditto.
> 	* gcc.target/riscv/sat_u_sub_imm-run-8.c: Ditto.
> 	* gcc.target/riscv/sat_u_sub_imm-5_3.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-6_3.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-7_3.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-8_1.c: New test.
This is fine once the prerequisite patch is installed.

Thanks,
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c
new file mode 100644
index 00000000000..42edfc59f8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_3.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if  "" { *-*-* } { "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm1_uint8_t_fmt_2:
+** snez\s+[atx][0-9]+,\s*a0
+** subw\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c
new file mode 100644
index 00000000000..5250b90418a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_3.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if  "" { *-*-* } { "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm1_uint16_t_fmt_2:
+** snez\s+[atx][0-9]+,\s*a0
+** subw\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 1)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c
new file mode 100644
index 00000000000..99df0e4b683
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_3.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if  "" { *-*-* } { "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm1_uint32_t_fmt_2:
+** snez\s+[atx][0-9]+,\s*a0
+** subw\s+a0,\s*a0,\s*[atx][0-9]+
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 1)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c
new file mode 100644
index 00000000000..cbbc08339f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8_1.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if  "" { *-*-* } { "-flto" } } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm1_uint64_t_fmt_2:
+** snez\s+[atx][0-9]+,\s*a0
+** sub\s+a0,\s*a0,\s*[atx][0-9]+
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_SUB" "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
index 627e81bca4b..fc3809590de 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
@@ -4,6 +4,7 @@ 
 #include "sat_arith.h"
 
 DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1)
 DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 2)
 DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 6)
 DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 129)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
index 8deed2bf28f..0f4f9e40f1f 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
@@ -4,6 +4,7 @@ 
 #include "sat_arith.h"
 
 DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 1)
 DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 2)
 DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 6)
 DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 32767)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
index 7a3d7b0176f..ea15d85782d 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
@@ -4,6 +4,7 @@ 
 #include "sat_arith.h"
 
 DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 1)
 DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2)
 DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 6)
 DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483647)
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c
index 3ed1c90f78f..612da9212cd 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c
@@ -4,6 +4,7 @@ 
 #include "sat_arith.h"
 
 DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1)
 DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 2)
 DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 6)
 DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 18446744073709551614u)