From patchwork Wed Oct 23 11:05:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yury Khrustalev X-Patchwork-Id: 99428 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3A3A53858C50 for ; Wed, 23 Oct 2024 11:13:33 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 34A933858C52; Wed, 23 Oct 2024 11:08:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 34A933858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 34A933858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729681741; cv=none; b=YsXIlSRZ2nugw+PrMPLYSGvjfLMAXtJ0mTzd1L2wTfTEgqrl/bPaqJ/WxhtBYc67HLO6649uSH8hyI7/XwQ6ObIR4vcrqD9Kn/Urpnzo1C/vzKePro7StiPHR+8/XZUVgNxLCjKLciRScpSd0gRyi/yjgMpFoVN6U6F7GvJVgGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1729681741; c=relaxed/simple; bh=x8Rs2pOxCkSaPfQjaJ4Lt2UppedOMJZlFWeNPLZflls=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=hfmkFjLiFy2393685lT07hEZGOCLPQK093vSSjv6Z4udI1mDErnrthCaF1dZp5ypIcQEobLEXOsCx5JUErd3kL+zccOrjvMg+1/BTfZK5f24G1Z8HR63o/SG14oXyU6AKapi6oThuEq9FzPqtH9HmqrctdH056bm9YHpQhR6f6I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B14AB339; Wed, 23 Oct 2024 04:09:26 -0700 (PDT) Received: from udebian.localdomain (unknown [10.1.39.30]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 57A573F528; Wed, 23 Oct 2024 04:08:56 -0700 (PDT) From: Yury Khrustalev To: gcc-patches@gcc.gnu.org Cc: nsz@gcc.gnu.org, richard.earnshaw@arm.com, matthieu.longo@arm.com, richard.ball@arm.com Subject: [PATCH 19/22] aarch64: Introduce indirect_return attribute Date: Wed, 23 Oct 2024 12:05:25 +0100 Message-Id: <20241023110528.487830-20-yury.khrustalev@arm.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241023110528.487830-1-yury.khrustalev@arm.com> References: <20241023110528.487830-1-yury.khrustalev@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_STOCKGEN, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Szabolcs Nagy Tail calls of indirect_return functions from non-indirect_return functions are disallowed even if BTI is disabled, since the call site may have BTI enabled. Following x86, mismatching attribute on function pointers is not a type error even though this can lead to bugs. Needed for swapcontext within the same function when GCS is enabled. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_gnu_attributes): Add indirect_return. (aarch64_function_ok_for_sibcall): Disallow tail calls if caller is non-indirect_return but callee is indirect_return. (aarch64_comp_type_attributes): Check indirect_return attribute. * config/arm/aarch-bti-insert.cc (call_needs_bti_j): New. (rest_of_insert_bti): Use call_needs_bti_j. --- gcc/config/aarch64/aarch64.cc | 11 +++++++++ gcc/config/arm/aarch-bti-insert.cc | 36 ++++++++++++++++++++++++++---- 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index a89a30113b9..9bfc9a1dbba 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -853,6 +853,7 @@ static const attribute_spec aarch64_gnu_attributes[] = affects_type_identity, handler, exclude } */ { "aarch64_vector_pcs", 0, 0, false, true, true, true, handle_aarch64_vector_pcs_attribute, NULL }, + { "indirect_return", 0, 0, false, true, true, false, NULL, NULL }, { "arm_sve_vector_bits", 1, 1, false, true, false, true, aarch64_sve::handle_arm_sve_vector_bits_attribute, NULL }, @@ -6429,6 +6430,14 @@ aarch64_function_ok_for_sibcall (tree, tree exp) if (bool (aarch64_cfun_shared_flags (state)) != bool (aarch64_fntype_shared_flags (fntype, state))) return false; + + /* BTI J is needed where indirect_return functions may return + if bti is enabled there. */ + if (lookup_attribute ("indirect_return", TYPE_ATTRIBUTES (fntype)) + && !lookup_attribute ("indirect_return", + TYPE_ATTRIBUTES (TREE_TYPE (cfun->decl)))) + return false; + return true; } @@ -29118,6 +29127,8 @@ aarch64_comp_type_attributes (const_tree type1, const_tree type2) if (!check_attr ("gnu", "aarch64_vector_pcs")) return 0; + if (!check_attr ("gnu", "indirect_return")) + return 0; if (!check_attr ("gnu", "Advanced SIMD type")) return 0; if (!check_attr ("gnu", "SVE type")) diff --git a/gcc/config/arm/aarch-bti-insert.cc b/gcc/config/arm/aarch-bti-insert.cc index 14d36971cd4..403afff9120 100644 --- a/gcc/config/arm/aarch-bti-insert.cc +++ b/gcc/config/arm/aarch-bti-insert.cc @@ -92,6 +92,35 @@ const pass_data pass_data_insert_bti = 0, /* todo_flags_finish. */ }; +/* Decide if BTI J is needed after a call instruction. */ +static bool +call_needs_bti_j (rtx_insn *insn) +{ + /* Call returns twice, one of which may be indirect. */ + if (find_reg_note (insn, REG_SETJMP, NULL)) + return true; + + /* Tail call does not return. */ + if (SIBLING_CALL_P (insn)) + return false; + + /* Check if the function is marked to return indirectly. */ + rtx call = get_call_rtx_from (insn); + rtx fnaddr = XEXP (call, 0); + tree fndecl = NULL_TREE; + if (GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF) + fndecl = SYMBOL_REF_DECL (XEXP (fnaddr, 0)); + if (fndecl == NULL_TREE) + fndecl = MEM_EXPR (fnaddr); + if (!fndecl) + return false; + if (TREE_CODE (TREE_TYPE (fndecl)) != FUNCTION_TYPE + && TREE_CODE (TREE_TYPE (fndecl)) != METHOD_TYPE) + return false; + tree fntype = TREE_TYPE (fndecl); + return lookup_attribute ("indirect_return", TYPE_ATTRIBUTES (fntype)); +} + /* Insert the BTI instruction. */ /* This is implemented as a late RTL pass that runs before branch shortening and does the following. */ @@ -147,10 +176,9 @@ rest_of_insert_bti (void) } } - /* Also look for calls to setjmp () which would be marked with - REG_SETJMP note and put a BTI J after. This is where longjump () - will return. */ - if (CALL_P (insn) && (find_reg_note (insn, REG_SETJMP, NULL))) + /* Also look for calls that may return indirectly, such as setjmp, + and put a BTI J after them. */ + if (CALL_P (insn) && call_needs_bti_j (insn)) { bti_insn = aarch_gen_bti_j (); emit_insn_after (bti_insn, insn);