diff mbox series

[v1,2/2] RISC-V: Add testcases for form 4 of signed scalar SAT_ADD

Message ID 20240920021720.582761-2-pan2.li@intel.com
State Committed
Commit 50c9c3cbdf26dfd2499b12eb6b9bc2218e598546
Headers
Series [v1,1/2] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD |

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Commit Message

Li, Pan2 Sept. 20, 2024, 2:17 a.m. UTC 
  From: Pan Li <pan2.li@intel.com>

Form 4:
  #define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)           \
  T __attribute__((noinline))                            \
  sat_s_add_##T##_fmt_4 (T x, T y)                       \
  {                                                      \
    T sum;                                               \
    bool overflow = __builtin_add_overflow (x, y, &sum); \
    return !overflow ? sum : x < 0 ? MIN : MAX;          \
  }

DEF_SAT_S_ADD_FMT_4 (int64_t, uint64_t, INT64_MIN, INT64_MAX)

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_s_add-13.c: New test.
	* gcc.target/riscv/sat_s_add-14.c: New test.
	* gcc.target/riscv/sat_s_add-15.c: New test.
	* gcc.target/riscv/sat_s_add-16.c: New test.
	* gcc.target/riscv/sat_s_add-run-13.c: New test.
	* gcc.target/riscv/sat_s_add-run-14.c: New test.
	* gcc.target/riscv/sat_s_add-run-15.c: New test.
	* gcc.target/riscv/sat_s_add-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h    | 14 ++++++++
 gcc/testsuite/gcc.target/riscv/sat_s_add-13.c | 30 +++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_s_add-14.c | 32 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_s_add-15.c | 31 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_s_add-16.c | 29 +++++++++++++++++
 .../gcc.target/riscv/sat_s_add-run-13.c       | 16 ++++++++++
 .../gcc.target/riscv/sat_s_add-run-14.c       | 16 ++++++++++
 .../gcc.target/riscv/sat_s_add-run-15.c       | 16 ++++++++++
 .../gcc.target/riscv/sat_s_add-run-16.c       | 16 ++++++++++
 9 files changed, 200 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c

Comments

Kito Cheng Sept. 22, 2024, 4:38 p.m. UTC | #1 
LGTM

<pan2.li@intel.com> 於 2024年9月20日 週五 10:21 寫道：

> From: Pan Li <pan2.li@intel.com>
>
> Form 4:
>   #define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)           \
>   T __attribute__((noinline))                            \
>   sat_s_add_##T##_fmt_4 (T x, T y)                       \
>   {                                                      \
>     T sum;                                               \
>     bool overflow = __builtin_add_overflow (x, y, &sum); \
>     return !overflow ? sum : x < 0 ? MIN : MAX;          \
>   }
>
> DEF_SAT_S_ADD_FMT_4 (int64_t, uint64_t, INT64_MIN, INT64_MAX)
>
> The below test are passed for this patch.
> * The rv64gcv fully regression test.
>
> It is test only patch and obvious up to a point, will commit it
> directly if no comments in next 48H.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/sat_arith.h: Add test helper macros.
>         * gcc.target/riscv/sat_s_add-13.c: New test.
>         * gcc.target/riscv/sat_s_add-14.c: New test.
>         * gcc.target/riscv/sat_s_add-15.c: New test.
>         * gcc.target/riscv/sat_s_add-16.c: New test.
>         * gcc.target/riscv/sat_s_add-run-13.c: New test.
>         * gcc.target/riscv/sat_s_add-run-14.c: New test.
>         * gcc.target/riscv/sat_s_add-run-15.c: New test.
>         * gcc.target/riscv/sat_s_add-run-16.c: New test.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/testsuite/gcc.target/riscv/sat_arith.h    | 14 ++++++++
>  gcc/testsuite/gcc.target/riscv/sat_s_add-13.c | 30 +++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/sat_s_add-14.c | 32 +++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/sat_s_add-15.c | 31 ++++++++++++++++++
>  gcc/testsuite/gcc.target/riscv/sat_s_add-16.c | 29 +++++++++++++++++
>  .../gcc.target/riscv/sat_s_add-run-13.c       | 16 ++++++++++
>  .../gcc.target/riscv/sat_s_add-run-14.c       | 16 ++++++++++
>  .../gcc.target/riscv/sat_s_add-run-15.c       | 16 ++++++++++
>  .../gcc.target/riscv/sat_s_add-run-16.c       | 16 ++++++++++
>  9 files changed, 200 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-14.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-15.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-16.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> index ab141bb1779..a2617b6db70 100644
> --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> @@ -153,6 +153,17 @@ sat_s_add_##T##_fmt_3 (T x, T y)
>  \
>  #define DEF_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \
>    DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)
>
> +#define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)           \
> +T __attribute__((noinline))                            \
> +sat_s_add_##T##_fmt_4 (T x, T y)                       \
> +{                                                      \
> +  T sum;                                               \
> +  bool overflow = __builtin_add_overflow (x, y, &sum); \
> +  return !overflow ? sum : x < 0 ? MIN : MAX;          \
> +}
> +#define DEF_SAT_S_ADD_FMT_4_WRAP(T, UT, MIN, MAX) \
> +  DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)
> +
>  #define RUN_SAT_S_ADD_FMT_1(T, x, y) sat_s_add_##T##_fmt_1(x, y)
>  #define RUN_SAT_S_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_1(T, x, y)
>
> @@ -162,6 +173,9 @@ sat_s_add_##T##_fmt_3 (T x, T y)
>  \
>  #define RUN_SAT_S_ADD_FMT_3(T, x, y) sat_s_add_##T##_fmt_3(x, y)
>  #define RUN_SAT_S_ADD_FMT_3_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_3(T, x, y)
>
> +#define RUN_SAT_S_ADD_FMT_4(T, x, y) sat_s_add_##T##_fmt_4(x, y)
> +#define RUN_SAT_S_ADD_FMT_4_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_4(T, x, y)
> +
>
>  /******************************************************************************/
>  /* Saturation Sub (Unsigned and Signed)
>      */
>
>  /******************************************************************************/
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
> new file mode 100644
> index 00000000000..0923764cde4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
> @@ -0,0 +1,30 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_s_add_int8_t_fmt_4:
> +** add\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7
> +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
> +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127
> +** neg\s+[atx][0-9]+,\s*[atx][0-9]+
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** slliw\s+a0,\s*a0,\s*24
> +** sraiw\s+a0,\s*a0,\s*24
> +** ret
> +*/
> +DEF_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-14.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-14.c
> new file mode 100644
> index 00000000000..5526a927ddb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-14.c
> @@ -0,0 +1,32 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_s_add_int16_t_fmt_4:
> +** add\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15
> +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
> +** li\s+[atx][0-9]+,\s*32768
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** neg\s+[atx][0-9]+,\s*[atx][0-9]+
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** slliw\s+a0,\s*a0,\s*16
> +** sraiw\s+a0,\s*a0,\s*16
> +** ret
> +*/
> +DEF_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-15.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-15.c
> new file mode 100644
> index 00000000000..af51da0d01f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-15.c
> @@ -0,0 +1,31 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_s_add_int32_t_fmt_4:
> +** add\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
> +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
> +** li\s+[atx][0-9]+,\s*-2147483648
> +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** neg\s+[atx][0-9]+,\s*[atx][0-9]+
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** sext\.w\s+a0,\s*a0
> +** ret
> +*/
> +DEF_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-16.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-16.c
> new file mode 100644
> index 00000000000..6d9b3e0dcf2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-16.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_s_add_int64_t_fmt_4:
> +** add\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
> +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
> +** li\s+[atx][0-9]+,\s*-1
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** neg\s+[atx][0-9]+,\s*[atx][0-9]+
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** ret
> +*/
> +DEF_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c
> new file mode 100644
> index 00000000000..94d48ef24f6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c
> @@ -0,0 +1,16 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-additional-options "-std=c99" } */
> +
> +#include "sat_arith.h"
> +#include "sat_arith_data.h"
> +
> +#define T1 int8_t
> +#define T2 uint8_t
> +
> +DEF_SAT_S_ADD_FMT_4_WRAP(T1, T2, INT8_MIN, INT8_MAX)
> +
> +#define DATA             TEST_BINARY_DATA_WRAP(T1, ssadd)
> +#define T                TEST_BINARY_STRUCT_DECL(T1, ssadd)
> +#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_4_WRAP(T1, x, y)
> +
> +#include "scalar_sat_binary_run_xxx.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c
> new file mode 100644
> index 00000000000..2e734502273
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c
> @@ -0,0 +1,16 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-additional-options "-std=c99" } */
> +
> +#include "sat_arith.h"
> +#include "sat_arith_data.h"
> +
> +#define T1 int16_t
> +#define T2 uint16_t
> +
> +DEF_SAT_S_ADD_FMT_4_WRAP(T1, T2, INT16_MIN, INT16_MAX)
> +
> +#define DATA             TEST_BINARY_DATA_WRAP(T1, ssadd)
> +#define T                TEST_BINARY_STRUCT_DECL(T1, ssadd)
> +#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_4_WRAP(T1, x, y)
> +
> +#include "scalar_sat_binary_run_xxx.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c
> new file mode 100644
> index 00000000000..ec3022dab8e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c
> @@ -0,0 +1,16 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-additional-options "-std=c99" } */
> +
> +#include "sat_arith.h"
> +#include "sat_arith_data.h"
> +
> +#define T1 int32_t
> +#define T2 uint32_t
> +
> +DEF_SAT_S_ADD_FMT_4_WRAP(T1, T2, INT32_MIN, INT32_MAX)
> +
> +#define DATA             TEST_BINARY_DATA_WRAP(T1, ssadd)
> +#define T                TEST_BINARY_STRUCT_DECL(T1, ssadd)
> +#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_4_WRAP(T1, x, y)
> +
> +#include "scalar_sat_binary_run_xxx.h"
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c
> new file mode 100644
> index 00000000000..911856ed60b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c
> @@ -0,0 +1,16 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-additional-options "-std=c99" } */
> +
> +#include "sat_arith.h"
> +#include "sat_arith_data.h"
> +
> +#define T1 int64_t
> +#define T2 uint64_t
> +
> +DEF_SAT_S_ADD_FMT_4_WRAP(T1, T2, INT64_MIN, INT64_MAX)
> +
> +#define DATA             TEST_BINARY_DATA_WRAP(T1, ssadd)
> +#define T                TEST_BINARY_STRUCT_DECL(T1, ssadd)
> +#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_4_WRAP(T1, x, y)
> +
> +#include "scalar_sat_binary_run_xxx.h"
> --
> 2.43.0
>
>
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ab141bb1779..a2617b6db70 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -153,6 +153,17 @@  sat_s_add_##T##_fmt_3 (T x, T y)                       \
 #define DEF_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \
   DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)
 
+#define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)           \
+T __attribute__((noinline))                            \
+sat_s_add_##T##_fmt_4 (T x, T y)                       \
+{                                                      \
+  T sum;                                               \
+  bool overflow = __builtin_add_overflow (x, y, &sum); \
+  return !overflow ? sum : x < 0 ? MIN : MAX;          \
+}
+#define DEF_SAT_S_ADD_FMT_4_WRAP(T, UT, MIN, MAX) \
+  DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)
+
 #define RUN_SAT_S_ADD_FMT_1(T, x, y) sat_s_add_##T##_fmt_1(x, y)
 #define RUN_SAT_S_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_1(T, x, y)
 
@@ -162,6 +173,9 @@  sat_s_add_##T##_fmt_3 (T x, T y)                       \
 #define RUN_SAT_S_ADD_FMT_3(T, x, y) sat_s_add_##T##_fmt_3(x, y)
 #define RUN_SAT_S_ADD_FMT_3_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_3(T, x, y)
 
+#define RUN_SAT_S_ADD_FMT_4(T, x, y) sat_s_add_##T##_fmt_4(x, y)
+#define RUN_SAT_S_ADD_FMT_4_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_4(T, x, y)
+
 /******************************************************************************/
 /* Saturation Sub (Unsigned and Signed)                                       */
 /******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
new file mode 100644
index 00000000000..0923764cde4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
@@ -0,0 +1,30 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_s_add_int8_t_fmt_4:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** xor\s+[atx][0-9]+,\s*a0,\s*a1
+** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7
+** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slliw\s+a0,\s*a0,\s*24
+** sraiw\s+a0,\s*a0,\s*24
+** ret
+*/
+DEF_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-14.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-14.c
new file mode 100644
index 00000000000..5526a927ddb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-14.c
@@ -0,0 +1,32 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_s_add_int16_t_fmt_4:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** xor\s+[atx][0-9]+,\s*a0,\s*a1
+** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15
+** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+** li\s+[atx][0-9]+,\s*32768
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slliw\s+a0,\s*a0,\s*16
+** sraiw\s+a0,\s*a0,\s*16
+** ret
+*/
+DEF_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-15.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-15.c
new file mode 100644
index 00000000000..af51da0d01f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-15.c
@@ -0,0 +1,31 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_s_add_int32_t_fmt_4:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** xor\s+[atx][0-9]+,\s*a0,\s*a1
+** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
+** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+** li\s+[atx][0-9]+,\s*-2147483648
+** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-16.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-16.c
new file mode 100644
index 00000000000..6d9b3e0dcf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-16.c
@@ -0,0 +1,29 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_s_add_int64_t_fmt_4:
+** add\s+[atx][0-9]+,\s*a0,\s*a1
+** xor\s+[atx][0-9]+,\s*a0,\s*a1
+** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63
+** li\s+[atx][0-9]+,\s*-1
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** neg\s+[atx][0-9]+,\s*[atx][0-9]+
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c
new file mode 100644
index 00000000000..94d48ef24f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 int8_t
+#define T2 uint8_t
+
+DEF_SAT_S_ADD_FMT_4_WRAP(T1, T2, INT8_MIN, INT8_MAX)
+
+#define DATA             TEST_BINARY_DATA_WRAP(T1, ssadd)
+#define T                TEST_BINARY_STRUCT_DECL(T1, ssadd)
+#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_4_WRAP(T1, x, y)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c
new file mode 100644
index 00000000000..2e734502273
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 int16_t
+#define T2 uint16_t
+
+DEF_SAT_S_ADD_FMT_4_WRAP(T1, T2, INT16_MIN, INT16_MAX)
+
+#define DATA             TEST_BINARY_DATA_WRAP(T1, ssadd)
+#define T                TEST_BINARY_STRUCT_DECL(T1, ssadd)
+#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_4_WRAP(T1, x, y)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c
new file mode 100644
index 00000000000..ec3022dab8e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 int32_t
+#define T2 uint32_t
+
+DEF_SAT_S_ADD_FMT_4_WRAP(T1, T2, INT32_MIN, INT32_MAX)
+
+#define DATA             TEST_BINARY_DATA_WRAP(T1, ssadd)
+#define T                TEST_BINARY_STRUCT_DECL(T1, ssadd)
+#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_4_WRAP(T1, x, y)
+
+#include "scalar_sat_binary_run_xxx.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c
new file mode 100644
index 00000000000..911856ed60b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 int64_t
+#define T2 uint64_t
+
+DEF_SAT_S_ADD_FMT_4_WRAP(T1, T2, INT64_MIN, INT64_MAX)
+
+#define DATA             TEST_BINARY_DATA_WRAP(T1, ssadd)
+#define T                TEST_BINARY_STRUCT_DECL(T1, ssadd)
+#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_4_WRAP(T1, x, y)
+
+#include "scalar_sat_binary_run_xxx.h"