From patchwork Fri Sep 20 02:17:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 97730 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AE27E3858D29 for ; Fri, 20 Sep 2024 02:19:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by sourceware.org (Postfix) with ESMTPS id 7105E3858D29 for ; Fri, 20 Sep 2024 02:18:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7105E3858D29 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7105E3858D29 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726798724; cv=none; b=I9Vnh1iLv0Xt2Qtaub0DoPnTe/u7jBE8sPF3IvZlmqfVVaJRNHMpnhmORQkHtcTKCAV/MGCIXVwoAq7W3FJ4SDl0/kWWwP36fBHM8Ewbl6o9vAXBw+gMHM4q+bxR3hsy9xusdhzYDnba62gslyY+7e5WLXF3Hclcq3mCZ6d/eRQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1726798724; c=relaxed/simple; bh=alQY6usd8t6tSzh/fnEF9vQfrYyUWLfvvuj5tVQZcOI=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=JnFUGJuHMtTYix064LmIlX484BxGmZnxPO2VMUm8XoAIk4j0dXOGPA7Ar6Rn4cWSA7P3uRXbdfG/vsjf7ry6JjD1i/PYWU38WE7QU54N6htzwvDM2MoQ5L299NL4QgqYck0jZof4Zq+mq3lGk6mgxlQQAmYrLYo+UTlrm1Ia8yc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1726798708; x=1758334708; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=alQY6usd8t6tSzh/fnEF9vQfrYyUWLfvvuj5tVQZcOI=; b=L4bYTWlrdnSiorDYwz+AivhVCKAomRvcT627SWJQkPAKYKTNaXc4MrlE YM6USEUbn7NQQykUubS7gh3EqMF2+VXmOYqMKmBF2KFI4S6A/PW4ucjXl saUiBiDFR7dFgeVzw6Ch09tKIHJbdZZ7svQTbiKUYSoeuj3zrr2JImplO qlLQmewNK6hgeDtOWaTn144N8dO9+zf6fNKnWCG0pZo18tMaMOOmykgWe lMes7ukTS3mfHJ9s1A9gkoMv3Tuuc82mvfLpOe4a+pc7RE3ETLGzJ76BF 95BF/ZVANl360cs2x1uXPOmmgweCCkBwaS5RlTDfrMVVu5X+OaNnUXB61 A==; X-CSE-ConnectionGUID: slAqAxi7RPCG1gL+cvyG+A== X-CSE-MsgGUID: pSmkUrd6QeqKQAE9LZtQnA== X-IronPort-AV: E=McAfee;i="6700,10204,11200"; a="25911285" X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="25911285" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2024 19:18:27 -0700 X-CSE-ConnectionGUID: O6mT9qvQQpyLKJvrc6Ni7Q== X-CSE-MsgGUID: nQOXop4FQv6bFhbmFvmGkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,243,1719903600"; d="scan'208";a="69995750" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa010.jf.intel.com with ESMTP; 19 Sep 2024 19:18:23 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 1/2] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD Date: Fri, 20 Sep 2024 10:17:19 +0800 Message-ID: <20240920021720.582761-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li This patch would like to add testcases of the signed scalar SAT_ADD for form 3. Aka: Form 3: #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ T __attribute__((noinline)) \ sat_s_add_##T##_fmt_3 (T x, T y) \ { \ T sum; \ bool overflow = __builtin_add_overflow (x, y, &sum); \ return overflow ? x < 0 ? MIN : MAX : sum; \ } DEF_SAT_S_ADD_FMT_3 (int64_t, uint64_t, INT64_MIN, INT64_MAX) The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add test helper macros. * gcc.target/riscv/sat_s_add-10.c: New test. * gcc.target/riscv/sat_s_add-11.c: New test. * gcc.target/riscv/sat_s_add-12.c: New test. * gcc.target/riscv/sat_s_add-9.c: New test. * gcc.target/riscv/sat_s_add-run-10.c: New test. * gcc.target/riscv/sat_s_add-run-11.c: New test. * gcc.target/riscv/sat_s_add-run-12.c: New test. * gcc.target/riscv/sat_s_add-run-9.c: New test. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/sat_arith.h | 14 ++++++++ gcc/testsuite/gcc.target/riscv/sat_s_add-10.c | 32 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_s_add-11.c | 31 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_s_add-12.c | 29 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/sat_s_add-9.c | 30 +++++++++++++++++ .../gcc.target/riscv/sat_s_add-run-10.c | 16 ++++++++++ .../gcc.target/riscv/sat_s_add-run-11.c | 16 ++++++++++ .../gcc.target/riscv/sat_s_add-run-12.c | 16 ++++++++++ .../gcc.target/riscv/sat_s_add-run-9.c | 16 ++++++++++ 9 files changed, 200 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-9.c diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h index b4fbf5dc662..ab141bb1779 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h @@ -142,12 +142,26 @@ sat_s_add_##T##_fmt_2 (T x, T y) \ return x < 0 ? MIN : MAX; \ } +#define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ +T __attribute__((noinline)) \ +sat_s_add_##T##_fmt_3 (T x, T y) \ +{ \ + T sum; \ + bool overflow = __builtin_add_overflow (x, y, &sum); \ + return overflow ? x < 0 ? MIN : MAX : sum; \ +} +#define DEF_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \ + DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) + #define RUN_SAT_S_ADD_FMT_1(T, x, y) sat_s_add_##T##_fmt_1(x, y) #define RUN_SAT_S_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_1(T, x, y) #define RUN_SAT_S_ADD_FMT_2(T, x, y) sat_s_add_##T##_fmt_2(x, y) #define RUN_SAT_S_ADD_FMT_2_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_2(T, x, y) +#define RUN_SAT_S_ADD_FMT_3(T, x, y) sat_s_add_##T##_fmt_3(x, y) +#define RUN_SAT_S_ADD_FMT_3_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_3(T, x, y) + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/ diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-10.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-10.c new file mode 100644 index 00000000000..45329619f9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-10.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_s_add_int16_t_fmt_3: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** xor\s+[atx][0-9]+,\s*a0,\s*a1 +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 +** li\s+[atx][0-9]+,\s*32768 +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slliw\s+a0,\s*a0,\s*16 +** sraiw\s+a0,\s*a0,\s*16 +** ret +*/ +DEF_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-11.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-11.c new file mode 100644 index 00000000000..e12bc2c042f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-11.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_s_add_int32_t_fmt_3: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** xor\s+[atx][0-9]+,\s*a0,\s*a1 +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 +** li\s+[atx][0-9]+,\s*-2147483648 +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** sext\.w\s+a0,\s*a0 +** ret +*/ +DEF_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-12.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-12.c new file mode 100644 index 00000000000..9146193493b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-12.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_s_add_int64_t_fmt_3: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** xor\s+[atx][0-9]+,\s*a0,\s*a1 +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 +** li\s+[atx][0-9]+,\s*-1 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** ret +*/ +DEF_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-9.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-9.c new file mode 100644 index 00000000000..4526eb700ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-9.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sat_arith.h" + +/* +** sat_s_add_int8_t_fmt_3: +** add\s+[atx][0-9]+,\s*a0,\s*a1 +** xor\s+[atx][0-9]+,\s*a0,\s*a1 +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 +** neg\s+[atx][0-9]+,\s*[atx][0-9]+ +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 +** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ +** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ +** slliw\s+a0,\s*a0,\s*24 +** sraiw\s+a0,\s*a0,\s*24 +** ret +*/ +DEF_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-10.c new file mode 100644 index 00000000000..08b961a6689 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-10.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 int16_t +#define T2 uint16_t + +DEF_SAT_S_ADD_FMT_3_WRAP(T1, T2, INT16_MIN, INT16_MAX) + +#define DATA TEST_BINARY_DATA_WRAP(T1, ssadd) +#define T TEST_BINARY_STRUCT_DECL(T1, ssadd) +#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_3_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-11.c new file mode 100644 index 00000000000..3611b6e2788 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-11.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 int32_t +#define T2 uint32_t + +DEF_SAT_S_ADD_FMT_3_WRAP(T1, T2, INT32_MIN, INT32_MAX) + +#define DATA TEST_BINARY_DATA_WRAP(T1, ssadd) +#define T TEST_BINARY_STRUCT_DECL(T1, ssadd) +#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_3_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-12.c new file mode 100644 index 00000000000..3eaa6c2d7ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-12.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 int64_t +#define T2 uint64_t + +DEF_SAT_S_ADD_FMT_3_WRAP(T1, T2, INT64_MIN, INT64_MAX) + +#define DATA TEST_BINARY_DATA_WRAP(T1, ssadd) +#define T TEST_BINARY_STRUCT_DECL(T1, ssadd) +#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_3_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-9.c new file mode 100644 index 00000000000..6d38e5f1092 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-run-9.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 int8_t +#define T2 uint8_t + +DEF_SAT_S_ADD_FMT_3_WRAP(T1, T2, INT8_MIN, INT8_MAX) + +#define DATA TEST_BINARY_DATA_WRAP(T1, ssadd) +#define T TEST_BINARY_STRUCT_DECL(T1, ssadd) +#define RUN_BINARY(x, y) RUN_SAT_S_ADD_FMT_3_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h"